Datasheet

Section 9 Timers
Rev. 6.00 Aug 04, 2006 page 322 of 680
REJ09B0145-0600
4. Register Configuration
Table 9.20 shows the register configuration of the asynchronous event counter.
Table 9.20 Asynchronous Event Counter Registers
Name Abbr. R/W Initial Value Address
Event counter control/status register ECCSR R/W H'00 H'FF95
Event counter H ECH R H'00 H'FF96
Event counter L ECL R H'00 H'FF97
Clock stop register 2 CKSTP2 R/W H'FF H'FFFB
9.7.2 Register Descriptions
1. Event Counter Control/Status Register (ECCSR)
OVH CUEL CRCH CRCLOVL — CH2 CUEH
76543210
0
0000000
R/(W)
*
R/W R/W R/W
R/(W)
*
R/W R/W
R/W
Bit
Initial Value
Read/Write
Note: * Bits 7 and 6 can only be written with 0, for flag clearing.
ECCSR is an 8-bit read/write register that controls counter overflow detection, counter resetting,
and halting of the count-up function.
ECCSR is initialized to H'00 upon reset.