Datasheet

Section 9 Timers
Rev. 6.00 Aug 04, 2006 page 325 of 680
REJ09B0145-0600
Bit 2: Count-up enable L (CUEL)
Bit 3 enables event clock input to ECL. When 1 is written to this bit, event clock input is enabled
and increments the counter. When 0 is written to this bit, event clock input is disabled and the
ECL value is held.
Bit 2
CUEL Description
0 ECL event clock input is disabled
ECL value is held
(initial value)
1 ECL event clock input is enabled
Bit 1: Counter reset control H (CRCH)
Bit 1 controls resetting of ECH. When this bit is cleared to 0, ECH is reset. When 1 is written to
this bit, the counter reset is cleared and the ECH count-up function is enabled.
Bit 1
CRCH Description
0 ECH is reset (initial value)
1 ECH reset is cleared and count-up function is enabled
Bit 0: Counter reset control L (CRCL)
Bit 0 controls resetting of ECL. When this bit is cleared to 0, ECL is reset. When 1 is written to
this bit, the counter reset is cleared and the ECL count-up function is enabled.
Bit 0
CRCL Description
0 ECL is reset (initial value)
1 ECL reset is cleared and count-up function is enabled