Datasheet

Section 10 Serial Communication Interface
Rev. 6.00 Aug 04, 2006 page 339 of 680
REJ09B0145-0600
SDRU read/write operations must only be performed after data transmission/reception has been
completed. Data contents are not guaranteed if read/write operations are executed while data
transmission/reception is in progress.
The value of SDRU is undefined upon reset.
4. Serial Data Register L (SDRL)
Bit
Initial value
Read/Write
7
SDRL7
Undefined
R/W
6
SDRL6
Undefined
R/W
5
SDRL5
Undefined
R/W
4
SDRL4
Undefined
R/W
3
SDRL3
Undefined
R/W
0
SDRL0
Undefined
R/W
2
SDRL2
Undefined
R/W
1
SDRL1
Undefined
R/W
SDRL is an 8-bit read/write register used as the data register in 8-bit transfer, and as the data
register for the lower 8 bits in 16-bit transfer (while SDRU is used for the upper 8 bits).
In 8-bit transfer, the data written into SDRL is output from the SO
1
pin in LSB-first order. In the
replacement process, data is input LSB-first from the SI
1
pin, and the data is shifted in the MSB →
LSB direction.
The operation in 16-bit transfer is the same as for 8-bit transfer, except that the input data is taken
from SDRU.
SDRL read/write operations must only be performed after data transmission/reception has been
completed. Data contents are not guaranteed if read/write operations are executed while data
transmission/reception is in progress.
The value of SDRL is undefined upon reset.
5. Clock Stop Register 1 (CKSTPR1)
S1CKSTP TFCKSTP TCCKSTP TACKSTPS31CKSTP S32CKSTP ADCKSTP TGCKSTP
76543210
1
1111111
R/W
R/W R/W R/W
R/W R/W R/W
R/W
Bit
Initial value
Read/Write
CKSTPR1 is an 8-bit read/write register that performs module standby mode control for peripheral
modules. Only the bit relating to SCI1 is described here. For details of the other bits, see the
sections on the relevant modules.