Datasheet

Section 10 Serial Communication Interface
Rev. 6.00 Aug 04, 2006 page 356 of 680
REJ09B0145-0600
Bits 1 and 0: Clock select 1, 0 (CKS1, CKS0)
Bits 1 and 0 choose φ/64, φ/16, φ/2, or φ as the clock source for the baud rate generator.
For the relation between the clock source, bit rate register setting, and baud rate, see 8, Bit rate
register (BRR).
Bit 1
CKS1
Bit 0
CKS0 Description
00φ clock (initial value)
01φ
W
/2 clock
*
1
/φ
W
clock
*
2
10φ/16 clock
11φ/64 clock
Notes: 1. φ
W
/2 clock is selected in active (medium- and high-speed) or sleep (medium- and high-
speed) mode.
2. φ
W
clock is selected in subactive or subsleep mode. SCI3 can be used only when the
φ
W
/2 is selected as the CPU clock in subactive or subsleep mode.
6. Serial Control Register 3 (SCR3)
Bit
Initial value
Read/Write
7
TIE
0
R/W
6
RIE
0
R/W
5
TE
0
R/W
4
RE
0
R/W
3
MPIE
0
R/W
0
CKE0
0
R/W
2
TEIE
0
R/W
1
CKE1
0
R/W
SCR3 is an 8-bit register for selecting transmit or receive operation, the asynchronous mode clock
output, interrupt request enabling or disabling, and the transmit/receive clock source.
SCR3 can be read or written by the CPU at any time.
SCR3 is initialized to H'00 upon reset, and in standby, watch or module standby mode.