Datasheet

Section 10 Serial Communication Interface
Rev. 6.00 Aug 04, 2006 page 360 of 680
REJ09B0145-0600
After setting bits CKE1 and CKE0, set the operating mode in the serial mode register (SMR).
For details on clock source selection, see table 10.12 in 10.3.3,1, Overview.
Bit 1 Bit 0 Description
CKE1 CKE0 Communication Mode Clock Source SCK
3X
Pin Function
0 0 Asynchronous Internal clock I/O port
*
1
Synchronous Internal clock Serial clock output
*
1
0 1 Asynchronous Internal clock Clock output
*
2
Synchronous Reserved
1 0 Asynchronous External clock Clock input
*
3
Synchronous External clock Serial clock input
1 1 Asynchronous Reserved
Synchronous Reserved
Notes: 1. Initial value
2. A clock with the same frequency as the bit rate is output.
3. Input a clock with a frequency 16 times the bit rate.
7. Serial Status Register (SSR)
Bit
Initial value
Read/Write
7
TDRE
1
R/(W)
6
RDRF
0
R/(W)
5
OER
0
R/(W)
4
FER
0
R/(W)
3
PER
0
R/(W)
0
MPBT
0
R/W
2
TEND
1
R
1
MPBR
0
R
*****
Note: * Only a write of 0 for flag clearing is possible.
SSR is an 8-bit register containing status flags that indicate the operational status of SCI3, and
multiprocessor bits.
SSR can be read or written by the CPU at any time, but only a write of 1 is possible to bits TDRE,
RDRF, OER, PER, and FER. In order to clear these bits by writing 0, 1 must first be read.
Bits TEND and MPBR are read-only bits, and cannot be modified.
SSR is initialized to H'84 upon reset, and in standby, module standby, or watch mode.