Datasheet

Section 10 Serial Communication Interface
Rev. 6.00 Aug 04, 2006 page 367 of 680
REJ09B0145-0600
Notes: 1. φ
W
/2 clock is selected in active (medium- and high-speed) or sleep
(medium- and high-speed) mode.
2. φ
W
clock is selected in subactive or subsleep mode. SCI3 can be used only
when the φ
W
/2 is selected as the CPU clock in subactive or subsleep mode.
3. The error in table 10.6 is the value obtained from the following equation, rounded to two
decimal places.
Error (%) =
B (rate obtained from n, N, OSC) — R (bit rate in left-hand column in table 10.6.)
R (bit rate in left-hand column in table 10.6.)
× 100
Table 10.8 shows the maximum bit rate for each frequency. The values shown are for active
(high-speed) mode.
Table 10.8 Maximum Bit Rate for Each Frequency (Asynchronous Mode)
Setting
OSC (MHz) Maximum Bit Rate (bit/s) n N
0.0384* 600 0 0
2 31250 0 0
2.4576 38400 0 0
4 62500 0 0
10 156250 0 0
16 250000 0 0
Note: * When SMR is set up to CKS1 = “0”, CKS0 = “1”.
Table 10.9 shows examples of BRR settings in synchronous mode. The values shown are for
active (high-speed) mode.