Datasheet

Section 12 A/D Converter
Rev. 6.00 Aug 04, 2006 page 421 of 680
REJ09B0145-0600
Bit 7: Clock select (CKS)
Bit 7 sets the A/D conversion speed.
Bit 7 Conversion Time (Active (High-Speed) Mode)
*
CKS Conversion Period φ
φφ
φ = 1 MHz φ
φφ
φ = 5 MHz
0 62/φ (initial value) 62 µs 12.4 µs
1 31/φ 31 µs —
Note: * For information on conversion time settings for which operation is guaranteed, see
section 15, Electrical Characteristics.
Bit 6: External trigger select (TRGE)
Bit 6 enables or disables the start of A/D conversion by external trigger input.
Bit 6
TRGE Description
0 Disables start of A/D conversion by external trigger (initial value)
1 Enables start of A/D conversion by rising or falling edge of external trigger at pin
ADTRG*
Note: * The external trigger (ADTRG) edge is selected by bit IEG4 of IEGR. See 1. IRQ edge
select register (IEGR) in section 3.3.2 for details.
Bits 5 and 4: Reserved bits
Bits 5 and 4 are reserved; they are always read as 1, and cannot be modified.