Datasheet

Section 1 Overview
Rev. 6.00 Aug 04, 2006 page 8 of 680
REJ09B0145-0600
P1
0
/TMOW
P1
1
/TMOFL
P1
2
/TMOFH
P1
3
/TMIG
P1
4
/IRQ
4
/ADTRG
P1
5
/IRQ
1
/TMIC
P1
6
/IRQ
2
P1
7
/IRQ
3
/TMIF
P3
0
/PWM
P3
1
/UD/EXCL
P3
2
P3
3
/SCK
31
P3
4
/RXD
31
P3
5
/TXD
31
P3
6
/AEVH
P3
7
/AEVL
P5
0
/WKP
0
/SEG
1
P5
1
/WKP
1
/SEG
2
P5
2
/WKP
2
/SEG
3
P5
3
/WKP
3
/SEG
4
P5
4
/WKP
4
/SEG
5
P5
5
/WKP
5
/SEG
6
P5
6
/WKP
6
/SEG
7
P5
7
/WKP
7
/SEG
8
P4
0
/SCK
32
P4
1
/RXD
32
P4
2
/TXD
32
P4
3
/IRQ
0
OSC
1
OSC
2
System clock
OSC
X
1
X
2
Sub clock
OSC
V
SS
V
SS
V
CC
CV
CC
RES TEST
H8/300L
CPU
ROM
(60 K, 48 K, 40 K, 32 K,
24 K, and 16 K)
RAM
(2 K and 1 K)
Timer A
Timer C
Timer F
Timer G
Serial
communication
interface 3-1
Serial
communication
interface 1
Serial
communication
interface 3-2
14-bit PWM
LCD
controller/driver
WDT
Asynchronous
counter
A/D (10-bit)
V
0
V
1
V
2
V
3
PA
3
/COM
4
PA
2
/COM
3
PA
1
/COM
2
PA
0
/COM
1
P8
7
/SEG
32
P8
6
/SEG
31
P8
5
/SEG
30
P8
4
/SEG
29
P8
3
/SEG
28
P8
2
/SEG
27
P8
1
/SEG
26
P8
0
/SEG
25
P7
7
/SEG
24
P7
6
/SEG
23
P7
5
/SEG
22
P7
4
/SEG
21
P7
3
/SEG
20
P7
2
/SEG
19
P7
1
/SEG
18
P7
0
/SEG
17
P6
7
/SEG
16
P6
6
/SEG
15
P6
5
/SEG
14
P6
4
/SEG
13
P6
3
/SEG
12
P6
2
/SEG
11
P6
1
/SEG
10
P6
0
/SEG
9
AV
CC
AV
SS
PB
0
/AN
0
PB
1
/AN
1
PB
2
/AN
2
PB
3
/AN
3
PB
4
/AN
4
PB
5
/AN
5
PB
6
/AN
6
PB
7
/AN
7
PC
0
/AN
8
PC
1
/AN
9
PC
2
/AN
10
PC
3
/AN
11
P2
0
/SCK
1
P2
1
/SI
1
P2
2
/SO
1
P2
3
P2
4
P2
5
P2
6
P2
7
P9
7
/SEG
40
P9
6
/SEG
39
P9
5
/SEG
38
P9
4
/SEG
37
P9
3
/SEG
36
P9
2
/SEG
35
P9
1
/SEG
34
P9
0
/SEG
33
LCD power
supply
Port APort 9Port 8Port 7Port 6
Port C
Note: When the on-chip emulator is used, pins P24, P25, P26, and P27 are reserved for use exclusively by the
emulator and therefore cannot be accessed by the user.
Port B
Port 2Port 3Port 4Port 5 Port 1
Figure 1.1 (2) Block Diagram (H8/38347 Group and H8/38447 Group)