Datasheet

Section 13 LCD Controller/Driver
Rev. 6.00 Aug 04, 2006 page 457 of 680
REJ09B0145-0600
Table 13.3 Output Levels
Data 0 0 1 1
M0101
Static Common output V
1
V
SS
V
1
V
SS
Segment output V
1
V
SS
V
SS
V
1
1/2 duty Common output V
2
, V
3
V
2
, V
3
V
1
V
SS
Segment output V
1
V
SS
V
SS
V
1
1/3 duty Common output V
3
V
2
V
1
V
SS
Segment output V
2
V
3
V
SS
V
1
1/4 duty Common output V
3
V
2
V
1
V
SS
Segment output V
2
V
3
V
SS
V
1
13.3.5 Operation in Power-Down Modes
In this LSI, the LCD controller/driver can be operated even in the power-down modes. The
operating state of the LCD controller/driver in the power-down modes is summarized in table
13.4.
In subactive mode, watch mode, and subsleep mode, the system clock oscillator stops, and
therefore, unless φw, φw/2, or φw/4 has been selected by bits CKS3 to CKS0, the clock will not be
supplied and display will halt. Since there is a possibility that a direct current will be applied to
the LCD panel in this case, it is essential to ensure that φw, φw/2, or φw/4 is selected. In active
(medium-speed) mode, the system clock is switched, and therefore CKS3 to CKS0 must be
modified to ensure that the frame frequency does not change.
Table 13.4 Power-Down Modes and Display Operation
Mode Reset Active Sleep Watch Subactive Subsleep Standb
y
Module
Standby
Clock
φ Runs Runs Runs Stops Stops Stops Stops Stops
*
4
φw Runs Runs Runs Runs Runs Runs Stops
*
1
Stops
*
4
Display ACT = “0” Stops Stops Stops Stops Stops Stops Stops
*
2
Stops
opera
ti
on
ACT = “1” Stops Functions Functions Functions
*
3
Functions
*
3
Functions
*
3
Stops
*
2
Stops
Notes: 1. The subclock oscillator does not stop, but clock supply is halted.
2. The LCD drive power supply is turned off regardless of the setting of the PSW bit.
3. Display operation is performed only if
φw, φw/2, or φw/4 is selected as the operating clock.
4. The clock supplied to the LCD stops.