Datasheet

Section 15 Electrical Characteristics
Rev. 6.00 Aug 04, 2006 page 528 of 680
REJ09B0145-0600
Values
Item Symbol
Applicable
Pins
Min Typ Max Unit Test Condition
Reference
Figure
Input pin low
width
t
IL
IRQ0
0
to
IRQ0
4
,
WKP
0
to
WKP
7
,
ADTRG,
TMIC,
TMIF, TMIG,
AEVL, AEVH
2— — t
cyc
t
subcyc
Figure
15.3
UD pin minimum
transition width
t
UDH
t
UDL
UD 4 — — t
cyc
t
subcyc
Figure
15.4
Notes: 1. Determined by the SA1 and SA0 bits in the system control register 2 (SYSCR2).
2. The figure in parentheses ( ) indicates the maximum fosc value when an external clock
is used.
3. Also applies to H8/38347 Group.
4. Also applies to H8/38447 Group.
Table 15.28 Serial Interface (SCI1) Timing
V
CC
= 2.7 V to 5.5 V, AV
CC
= 2.7 V to 5.5 V, V
SS
= AV
SS
= 0.0 V unless otherwise indicated
Applicable
Values
Reference
Item Symbol Pins Min Typ Max Unit Test Condition Figure
Input clock cycle t
Scyc
SCK
1
4 ——t
cyc
Figure 15.5
Input clock high
width
t
SCKH
SCK
1
0.4——t
Scyc
Figure 15.5
Input clock low
width
t
SCKL
SCK
1
0.4——t
Scyc
Figure 15.5
Input clock rise
time
t
SCKr
SCK
1
— — 60.0 ns Figure 15.5
*
Input clock fall
time
t
SCKf
SCK
1
— — 60.0 ns Figure 15.5
*
Serial output
data delay time
t
SOD
SO
1
— — 200.0 ns Figure 15.5
*
Serial input data
setup time
t
SIS
SI
1
200.0 — — ns Figure 15.5
*
Serial input data
hold time
t
SIH
SI
1
200.0 — — ns Figure 15.5
*