Datasheet

Section 15 Electrical Characteristics
Rev. 6.00 Aug 04, 2006 page 536 of 680
REJ09B0145-0600
V
IL
V
IH
t
UDL
UD
t
UDH
Figure 15.4 UD Pin Minimum Modulation Width Timing
SCK
1
SO
1
SI
1
t
scyc
V
IH
or V
OH
*
V
IL
or V
OL
*
t
SOD
t
SCKf
t
SCKr
t
SCKL
t
SCKH
t
SIS
t
SIH
V
OH
*
V
OL
*
Note: * Output timing reference levels
See fi
g
ure 15.9 for the load conditions.
Output high level
Output low level
V
OH
= 1/2 V
CC
+ 0.2 V
V
OL
= 0.8 V
Figure 15.5 SCI1 Input/Output Timing