Datasheet

Appendix A CPU Instruction Set
Rev. 6.00 Aug 04, 2006 page 543 of 680
REJ09B0145-0600
Appendix A CPU Instruction Set
A.1 Instructions
Operation Notation
Rd8/16 General register (destination) (8 or 16 bits)
Rs8/16 General register (source) (8 or 16 bits)
Rn8/16 General register (8 or 16 bits)
CCR Condition code register
N N (negative) flag in CCR
Z Z (zero) flag in CCR
V V (overflow) flag in CCR
C C (carry) flag in CCR
PC Program counter
SP Stack pointer
#xx: 3/8/16 Immediate data (3, 8, or 16 bits)
d: 8/16 Displacement (8 or 16 bits)
@aa: 8/16 Absolute address (8 or 16 bits)
+ Addition
– Subtraction
× Multiplication
÷ Division
∧ Logical AND
∨ Logical OR
⊕ Exclusive logical OR
→ Move
— Logical complement
Condition Code Notation
Symbol
↔
Modified according to the instruction result
* Not fixed (value not guaranteed)
0 Always cleared to 0
— Not affected by the instruction execution result