Datasheet

Appendix A CPU Instruction Set
Rev. 6.00 Aug 04, 2006 page 549 of 680
REJ09B0145-0600
Addressing Mode/
Instruction Length (bytes) Condition Code
Mnemonic
Operand Size
Operation
#
xx: 8/16
Rn
@Rn
@(d:16, Rn)
@–Rn/@Rn+
@aa: 8/16
@(d:8, PC)
@@aa
Implied
I HNZ VC
No. of States
JMP @Rn — PC ← Rn16 2 ——————4
JMP @aa:16 — PC ← aa:16 4 ——————6
JMP @@aa:8 — PC ← @aa:8 2 ——————8
BSR d:8 — SP–2 → SP
PC → @SP
PC ← PC+d:8
2 ——————6
JSR @Rn — SP–2 → SP
PC → @SP
PC ← Rn16
2 ——————6
JSR @aa:16 — SP–2 → SP
PC → @SP
PC ← aa:16
4 ——————8
JSR @@aa:8 SP–2 → SP
PC → @SP
PC ← @aa:8
2 ——————8
RTS — PC ← @SP
SP+2 → SP
2 ——————8
RTE — CCR ← @SP
SP+2 → SP
PC ← @SP
SP+2 → SP
2
↔ ↔ ↔ ↔ ↔ ↔
1
0
SLEEP — Transit to sleep mode. 2 — —————2
LDC #xx:8, CCR B #xx:8 → CCR 2
↔ ↔ ↔ ↔ ↔ ↔
2
LDC Rs, CCR B Rs8 → CCR 2
↔ ↔ ↔ ↔ ↔ ↔
2
STC CCR, Rd B CCR → Rd8 2 ——————2
ANDC #xx:8, CCR B CCR∧#xx:8 → CCR 2
↔ ↔ ↔ ↔ ↔ ↔
2
ORC #xx:8, CCR B CCR∨#xx:8 → CCR 2
↔ ↔ ↔ ↔ ↔ ↔
2
XORC #xx:8, CCR B CCR⊕#xx:8 → CCR 2
↔ ↔ ↔ ↔ ↔ ↔
2
NOP — PC ← PC+2 2 ——————2
EEPMOV — if R4L≠0
Repeat @R5 → @R6
R5+1 → R5
R6+1 → R6
R4L–1 → R4L
Until R4L=0
else next;
4 ——————(4)
Notes: (1) Set to 1 when there is a carry or borrow from bit 11; otherwise cleared to 0.
(2) If the result is zero, the previous value of the flag is retained; otherwise the flag is
cleared to 0.