Datasheet

Appendix A CPU Instruction Set
Rev. 6.00 Aug 04, 2006 page 554 of 680
REJ09B0145-0600
Table A.3 Number of Cycles in Each Instruction
Execution Status Access Location
(instruction cycle) On-Chip Memory On-Chip Peripheral Module
Instruction fetch S
I
2—
Branch address read S
J
Stack operation S
K
Byte data access S
L
2 or 3
*
Word data access S
M
—
Internal operation S
N
1
Note: * Depends on which on-chip module is accessed. See section 2.9.1, Notes on Data
Access for details.