Datasheet

Appendix B Internal I/O Registers
Rev. 6.00 Aug 04, 2006 page 571 of 680
REJ09B0145-0600
ECCSR—Event Counter Control/Status Register H'95 AEC
Bit
Initial value
Read/Write
Note: * Only a write of 0 for clearing is possible.
7
OVH
0
R/(W)
*
6
OVL
0
R/(W)
*
5

0
R/W
0
CRCL
0
R/W
2
CUEL
0
R/W
1
CRCH
0
R/W
4
CH2
0
R/W
Counter reset control L
0
1
ECL is reset
ECL reset is cleared
and count-up function
is enabled
Counter reset control H
0
ECH is reset
1 ECH reset is cleared and
count-up function is enabled
Count-up enable L
0
ECL event clock input is disabled.
ECL value is held
1 ECL event clock input is enabled
Count-up enable H
0
ECH event clock input is disabled.
ECH value is held
1 ECH event clock input is enabled
Channel select
0
ECH and ECL are used together as a single-
channel 16-bit event counter
1 ECH and ECL are used as two independent
8-bit event counter channels
Counter overflow L
0
ECL has not overflowed
Clearing condition:
After readng OVL = 1, cleared by writing 0 to OVL
1 ECL has overflowed
Setting condition:
Set when ECL overflows from H'FF to H'00 while CH2 is set to 1
Counter overflow H
0
ECH has not overflowed
Clearing condition:
After readng OVH = 1, cleared by writing 0 to OVH
1 ECH has overflowed
Setting condition:
Set when ECH overflows from H'FF to H'00
3
CUEH
0
R/W