Datasheet

Appendix B Internal I/O Registers
Rev. 6.00 Aug 04, 2006 page 577 of 680
REJ09B0145-0600
SSR31—Serial Status Register31 H'9C SCI3
Bit
Initial value
Read/Write
Note: * Only a write of 0 for flag clearing is possible.
7
TDRE31
1
R/(W)
6
RDRF31
0
R/(W)
5
OER31
0
R/(W)
0
MPBT31
0
R/W
2
TEND31
1
R
1
MPBR31
0
R
4
FER31
0
R/(W)
Receive data register full
0
There is no receive data in RDR31
[Clearing conditions]
• After reading RDRF31 = 1, cleared by writing 0 to RDRF31
• When RDR31 data is read by an instruction
1
There is receive data in RDR31
[Setting condition] When reception ends normally and receive data is transferred from RSR31 to RDR31
Transmit data register empty
0
Transmit data written in TDR31 has not been transferred to TSR31
[Clearing conditions]
• After reading TDRE31 = 1, cleared by writing 0 to TDRE31
• When data is written to TDR31 by an instruction
1 Transmit data has not been written to TDR31, or transmit data written in TDR31 has been transferred to TSR31
[Setting conditions] • When bit TE in serial control register 31 (SCR31) is cleared to 0
• When data is transferred from TDR31 to TSR31
Transmit end
0
Transmission in progress
[Clearing conditions]
1
Transmission ended
[Setting conditions]
Parity error
0
Reception in progress or completed normally
[Clearing condition] After reading PER31 = 1, cleared by writing 0 to PER31
1
A parity error has occurred during reception
[Setting condition]
Framing error
0
Reception in progress or completed normally
[Clearing condition] After reading FER31 = 1, cleared by writing 0 to FER31
1
A framing error has occurred during reception
[Setting condition] When the stop bit at the end of the receive data is checked for a value of 1 at completion of
reception, and the stop bit is 0
Overrun error
0
Reception in progress or completed
[Clearing condition] After reading OER31 = 1, cleared by writing 0 to OER31
1 An overrun error has occurred during reception
[Setting condition] When the next serial reception is completed with RDRF31 set to 1
Multiprocessor bit receive
Multiprocessor bit transfer
0
Data in which the multiprocessor bit is 0 has been received
1 Data in which the multiprocessor bit is 1 has been received
0 A 0 multiprocessor bit is transmitted
1 A 1 multiprocessor bit is transmitted
3
PER31
0
R/(W)
*****
• After reading TDRE31 = 1, cleared by writing 0 to TDRE
• When data is written to TDR31 by an instruction
• When bit TE in serial control register 31 (SCR31) is cleared to 0
• When bit TDRE31 is set to 1 when the last bit of a transmit character is sent
When the number of 1 bits in the receive data plus parity bit does not match the parity
designated by the parity mode bit (PM31) in the serial mode register (SMR31)