Datasheet

Appendix B Internal I/O Registers
Rev. 6.00 Aug 04, 2006 page 588 of 680
REJ09B0145-0600
TMA—Timer Mode Register A H'B0 Timer A
Bit
Initial value
Read/Write
Note * Values when the CWOS bit in CWOSR is cleared to 0. When the CWOS bit is set to 1,
φw is output regardless of the value of bits TMA7 to TMA5.
7
TMA7
0
R/W
6
TMA6
0
R/W
5
TMA5
0
R/W
0
TMA0
0
R/W
2
TMA2
0
R/W
1
TMA1
0
R/W
Internal clock select
TMA3
TMA2
0 PSS
PSS
PSS
PSS
0
4
—
1
—
Clock output select*
0 φ/32
φ/16
TMA1
0
1
TMA0
0
0
0
0
001
0
1
0
0
0
1
PSS
PSS
PSS
PSS
10
1
0
0
10
0
10
1
0
11
1
1 PSW
PSW
PSW
PSW
00
1
0
1
00
1
00
1
1
0
1
1
1
PSW and TCA are reset
10
1
0
1
10
1
1
0
1
1
1
1
1
Prescaler and Divider Ratio
or Overflow Period
φ/8192
φ/4096
φ/2048
φ/512
φ/256
φ/128
φ/32
φ/8
1 s
0.5 s
0.25 s
0.03125 s
Interval
timer
Time
base
(when
using
32.768 kHz)
Function
0 0
00
001
φ/8
φ/4
1
01
1
1 00
101
1
10
1
11
φ /32
W
φ /16
W
φ /8
W
φ /4
W
3
TMA3
0
R/W