Datasheet

Appendix B Internal I/O Registers
Rev. 6.00 Aug 04, 2006 page 590 of 680
REJ09B0145-0600
TCSRW—Timer Control/Status Register W H'B2 Watchdog timer
Bit
Initial value
Read/Write
7
B6WI
1
R
6
TCWE
0
R/(W)
5
B4WI
1
R
4
TCSRWE
0
R/(W)
3
B2WI
1
R
0
WRST
0
R/(W)
2
WDON
0
R/(W)
1
B0WI
1
R
*** *
Watchdog timer reset
0 [Clearing conditions]
1 [Setting condition]
When TCW overflows and a reset signal is generated
• Reset by RES pin
• When TCSRWE = 1, and 0 is written in both B0WI and WRST
Bit 0 write inhibit
0 Bit 0 is write-enabled
Bit 0 is write-protected
1
Watchdog timer on
0 Watchdog timer operation is disabled
Watchdog timer operation is enabled
1
Bit 2 write inhibit
0 Bit 2 is write-enabled
Bit 2 is write-protected
1
Timer control/status register W write enable
0 Data cannot be written to bits 2 and 0
Data can be written to bits 2 and 0
1
Bit 4 write inhibit
0 Bit 4 is write-enabled
Bit 4 is write-protected
1
Timer counter W write enable
0 Data cannot be written to TCW
Data can be written to TCW
1
Bit 6 write inhibit
0 Bit 6 is write-enabled
Bit 6 is write-protected
1
Note: * Write is
p
ermitted onl
y
under certain conditions.