Datasheet

Appendix B Internal I/O Registers
Rev. 6.00 Aug 04, 2006 page 597 of 680
REJ09B0145-0600
TMG—Timer Mode Register G H'BC Timer G
Bit
Initial value
Read/Write
7
OVFH
0
R/(W)*
6
OVFL
0
R/(W)*
5
OVIE
0
W
3
CCLR1
0
W
0
CKS0
0
W
2
CCLR0
0
W
1
CKS1
0
W
4
IIEGS
0
W
Timer overflow flag H
Counter clear
TCG clearing is disabled
TCG cleared by falling edge of input capture input signal
TCG cleared by rising edge of input capture input signal
TCG cleared by both edges of input capture input signal
0
1
0
1
0
0
1
1
Timer overflow interrupt enable
TCG overflow interrupt request is disabled
TCG overflow interrupt request is enabled
0
1
0
[Clearing condition]
After reading OVFH = 1, cleared by writing 0 to OVFH
1 [Setting condition]
Set when TCG overflows from H'FF to H'00
Note: * Bits 7 and 6 can only be written with 0, for flag clearing.
Timer overflow flag L
0
[Clearing condition]
After reading OVFL = 1, cleared by writing 0 to OVFL
1 [Setting condition]
Set when TCG overflows from H'FF to H'00
Input capture interrupt edge select
0 Interrupt generated on rising edge of input capture input signal
1 Interrupt generated on falling edge of input capture input signal
Clock select
0 Internal clock: counting on
φ/64
0 Internal clock: counting on φ/32
0
1
1 Internal clock: counting on φ/2
1 Internal clock: counting on
φw/4
0
1