Datasheet
Appendix B Internal I/O Registers
Rev. 6.00 Aug 04, 2006 page 610 of 680
REJ09B0145-0600
PWCR—PWM Control Register H'D0 14-bit PWM
Bit
Initial value
Read/Write
7
1
6
1
5
1
4
1
3
1
0
PWCR0
0
W
2
1
1
PWCR1
0
W
Clock select
0 The input clock is φ/2 (tφ* = 2/φ)
The conversion period is 16,384/φ, with a minimum modulation width of 1/φ
The input clock is φ/4 (tφ* = 4/φ)
The conversion period is 32,768/φ, with a minimum modulation width of 2/φ
1
The input clock is φ/8 (tφ* = 8/φ)
The conversion period is 65,536/φ, with a minimum modulation width of 4/φ
The input clock is φ/16 (tφ* = 16/φ)
The conversion period is 131,072/φ, with a minimum modulation width of 8/φ
Note: tφ: Period of PWM input clock
*
PWDRU—PWM Data Register U H'D1 14-bit PWM
Bit
Initial value
Read/Write
7
—
1
—
6
—
1
—
5
0
W
4
0
W
3
0
W
0
0
W
2
0
W
1
0
W
Upper 6 bits of data for generating PWM waveform
PWDRU5 PWDRU4 PWDRU3 PWDRU0PWDRU2 PWDUR1
PWDRL—PWM Data Register L H'D2 14-bit PWM
Bit
Initial value
Read/Write
7
0
W
6
0
W
5
0
W
4
0
W
3
0
W
0
0
W
2
0
W
1
0
W
Lower 8 bits of data for generating PWM waveform
PWDRL5 PWDRL4 PWDRL3 PWDRL0PWDRL2 PWDRL1PWDRL6PWDRL7