Datasheet

Appendix B Internal I/O Registers
Rev. 6.00 Aug 04, 2006 page 620 of 680
REJ09B0145-0600
SYSCR1—System Control Register 1 H'F0 System control
Bit
Initial value
Read/Write
7
SSBY
0
R/W
6
STS2
0
R/W
5
STS1
0
R/W
3
LSON
0
R/W
0
MA0
1
R/W
2

1

1
MA1
1
R/W
4
STS0
0
R/W
Software standby
0 • When a SLEEP instruction is executed in active mode, a transition is
made to sleep mode
1
Standby timer select 2 to 0
0 Wait time = 8,192 states
Wait time = 16,384 states
0
0
1
Wait time = 32,768 states
Wait time = 65,536 states
10
1
Active (medium-speed)
mode clock select
φ /16
φ /32
0
1
0
0
1
1
φ /64
φ /128
1
1
00
10
1
Wait time = 131,072 states
Wait time = 2 states
Wait time = 8 states
Wait time = 16 states
Low speed on flag
0 The CPU operates on the system clock (φ)
1 The CPU operates on the subclock (φ )
SUB
• When a SLEEP instruction is executed in subactive mode, a transition
is made to subsleep mode
• When a SLEEP instruction is executed in active mode, a transition is
made to standby mode or watch mode
• When a SLEEP instruction is executed in subactive mode, a transition
is made to watch mode
osc
osc
osc
osc