Datasheet

Appendix B Internal I/O Registers
Rev. 6.00 Aug 04, 2006 page 625 of 680
REJ09B0145-0600
IRR1—Interrupt Request Register 1 H'F6 System control
Bit
Initial value
Read/Write
7
IRRTA
0
R/(W)
*
6
IRRS1
0
R/(W)
*
5

1

3
IRRI3
0
R/(W)
*
0
IRRI0
0
R/(W)
*
2
IRRI2
0
R/(W)
*
1
IRRI1
0
R/(W)
*
4
IRRI4
0
R/(W)
*
IRQ4 to IRQ0 interrupt request flags
0 [Clearing condition]
When IRRIn = 1, it is cleared by writing 0
(n = 4 to 0)
Note: * Bits 7, 6, and 4 to 0 can onl
y
be written with 0, for fla
g
clearin
g
.
1 [Setting condition]
When pin IRQn is designated for interrupt
input and the designated signal edge is input
Timer A interrupt request flag
0 [Clearing condition]
When IRRTA = 1, it is cleared by writing 0
1 [Setting condition]
When the timer A counter value overflows (from H'FF to H'00)
SCI1 interrupt request flag
0 [Clearing condition]
When IRRS1 = 1, it is cleared by writing 0
1 [Setting condition]
When SCI1 completes transfer