Datasheet

Appendix B Internal I/O Registers
Rev. 6.00 Aug 04, 2006 page 629 of 680
REJ09B0145-0600
CKSTPR2—Clock Stop Register 2 H'FB System control
Bit
Initial value
Read/Write
7
—
1
—
6
—
1
—
5
—
1
—
3
AECKSTP
1
R/W
0
LDCKSTP
1
R/W
2
WDCKSTP
1
R/W
1
PWCKSTP
1
R/W
4
—
1
—
LCD module standby mode control
WDT module standby mode control
0 WDT is set to module standby mode
WDT module standby mode is cleared
1
Asynchronous event counter module standby mode control
0 Asynchronous event counter is set to module standby mode
Asynchronous event counter module standby mode is cleared
1
PWM module standby mode control
0 PWM is set to module standby mode
PWM module standby mode is cleared
1
0 LCD is set to module standby mode
LCD module standby mode is cleared
1