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Hitachi Microcomputer Technical Q & A H8/300H Series Application Notes Hitachi Micro Systems, Incorporated 1994 ADE-502-038
When using this document, keep the following in mind: 1. This document may, wholly or partially, be subject to change without notice. 2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without Hitachi’s permission. 3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons during operation of the user’s unit according to this document. 4.
Introduction The H8/300H series microcontrollers are high-performance Hitachi-original 16-bit microcontrollers that build in the optimum peripheral equipment for industrial machinery around high-speed H8/300 CPUs that have architecture upwardly compatible with H8/300 CPUs.
Table 0-1 H8/300H Series Item H8/3003 H8/3002 H8/3001 H8/3042 H8/3041 H8/3040 CPU H8/300H H8/300H H8/300H H8/300H H8/300H H8/300H Mask (byte) — — — 64 k 48 k 32 k ZTAT * — — — Yes — — 512 512 512 2k 2k 2k Memory ROM RAM (byte) Address space (byte) 16 M 16 M 16 M 16 M 16 M 16 M External data bus width (bit) 8/16 8/16 8/16 8/16 8/16 8/16 Timers ITU (integrated timer unit) 5 ch 5 ch 5 ch 5 ch 5 ch 5 ch Watchdog timer 1 ch 1 ch — 1 ch 1 ch 1 ch
Table I-1 H8/300H Series (cont) Item CPU H8/3048 H8/3047 H8/3044 H8/3032 H8/3031 H8/3030 H8/300H H8/300H H8/300H H8/300H H8/300H H8/300H Mask (byte) 128 k 96 k 32 k 64 k 32 k 16 k ZTAT * Yes — — Yes — — 4k 4k 2k 2k 1k 512 Address space (byte) 16 M 16 M 16 M 1M 1M 1M External data bus width (bit) 8/16 8/16 8/16 8 8 8 Timers ITU (integrated timer unit) 5 ch 5 ch 5 ch 5 ch 5 ch 5 ch Watchdog timer 1 ch 1 ch 1 ch 1 ch 1 ch 1 ch DMA controller Mem
For Users of the Microcontroller Technical Q & A This Microcontroller Technical Q & A was compiled from answers to technical questions we received from Hitachi microcontroller users. We hope that it will be a useful addition to the H8/300H series user manuals. Before starting design of products that use microcontrollers, read through the manual to deepen your understanding of microcontroller products and re-familiarize yourself with those areas of difficulty at the design stage.
Contents Q&A No.
Q&A No.
Q&A No.
Section 1 CPU Technical Questions and Answers Product H8/300H Q&A No.
Technical Questions and Answers Product H8/300H Q&A No. Topic The Relationship Between Data Size and V Flag Changes QA300H-002A Question Classification—H8/300H Do the changes in the CCR’s V flag vary with data size? Software o Registers Bus controller Interrupts Resets Power-down mode Instructions Miscellaneous DMA controller ITU Watchdog timer SCI A/D converter I/O ports Related Manuals Answer The CCR’s V flag changes when an overflow is detected in the result of a signed arithmetic operation.
Technical Questions and Answers Product H8/300H Q&A No. Topic Use of General Registers QA300H-003A Question Classification—H8/300H Can different general registers be used as 8-bit, 16-bit, and 32-bit registers at the same time? Software o Registers Bus controller Interrupts Resets Power-down mode Instructions Miscellaneous DMA controller ITU Watchdog timer SCI A/D converter I/O ports Related Manuals Answer Yes. Registers can be set freely for use as shown in figure 1.3.
Technical Questions and Answers Product H8/300H Q&A No. Topic Bus State While the CPU Is Operating QA300H-004 Question 1. Classification—H8/300H Software What is the bus state during CPU internal processing? 2. What is the bus state after DREQ is received? 3.
Technical Questions and Answers Product H8/300H Topic Bus Modes Q&A No. QA300H-005A Question Classification—H8/300H Section 6.2.1 of the H8/3003 Hardware Manual says, “When even 1 bit of the ABWCR is cleared to 0, the bus mode becomes 16 bits.” Does this mean that all areas can be accessed in 16-bit mode? Software Registers o Bus controller Interrupts Resets Power-down mode Instructions Miscellaneous DMA controller ITU Watchdog timer SCI A/D converter I/O ports Related Manuals Answer No.
Technical Questions and Answers Product H8/300H Topic Setting the Bus Controller in Area 7 Q&A No.
Technical Questions and Answers Product H8/300H Q&A No. Topic External Installation of RAM to 8-Bit Bus Areas QA300H-007A Question Classification—H8/300H When RAM is externally installed in 8-bit bus space, which signal should be used to access it, HWR or LWR? Software Registers o Bus controller Interrupts Resets Power-down mode Instructions Miscellaneous DMA controller ITU Watchdog timer SCI A/D converter I/O ports Related Manuals Answer Manual Title Use the HWR signal.
Technical Questions and Answers Product H8/300H Q&A No. Topic Changing the Number of Wait States Inserted Per Area QA300H-008A-1 Question 1. 2.
Technical Questions and Answers Product H8/300H Q&A No. QA300H-008A-2 Topic Changing the Number of Wait States Inserted Per Area Answer Example: To set the following access states for the following areas: • Areas 0–1: 2 states • Area 2: 3 states • Areas 3–4: 4 states • Area 5: 5 states • Areas 6–7: 6 states Table 1.
Technical Questions and Answers Product H8/300H Topic Receiving BREQ in Power-Down Mode Q&A No. QA300H-009A Question 1. 2. Classification—H8/300H Software Can BREQ be received in sleep mode? Registers Can BREQ be received in hardware/software standby mode? o Bus controller Interrupts Resets Power-down mode Instructions Miscellaneous DMA controller ITU Watchdog timer SCI A/D converter I/O ports Related Manuals Answer Manual Title 1. Yes 2.
Technical Questions and Answers Product H8/300H Topic Maximum Wait Time After BREQ Input Q&A No. QA300H-010A Question Classification—H8/300H Software Why does it take so long between BREQ input and BACK output? Registers o Bus controller Interrupts Resets Power-down mode Instructions Miscellaneous DMA controller ITU Watchdog timer SCI A/D converter I/O ports Related Manuals Answer Because the BREQ request is held in the following cases: 1.
Technical Questions and Answers Product H8/300H Topic Interrupt Sampling Q&A No. QA300H-011A Question Classification—H8/300H Software When are external interrupts (NMI, IRQn) sampled? Registers Bus controller o Interrupts Resets Power-down mode Instructions Miscellaneous DMA controller ITU Watchdog timer SCI A/D converter I/O ports Related Manuals Answer Sampling occurs at every fall of the system clock φ. Manual Title Other Technical Documentation Document Name See figure 18.
Technical Questions and Answers Product H8/300H Topic Holding External Interrupts Q&A No. QA300H-012A Question 1. 2.
Technical Questions and Answers Product H8/300H Topic Receiving NMIs During NMI Processing Q&A No.
Technical Questions and Answers Product H8/300H Q&A No. Topic Edge Rise and Fall Times for Interrupt Pins QA300H-014A Question Classification—H8/300H Software When an edge trigger is used for an external interrupt, what are the longest allowed rise and fall times of the edge? Registers Bus controller o Interrupts Resets Power-down mode Instructions Miscellaneous DMA controller ITU Watchdog timer SCI A/D converter I/O ports Related Manuals Answer Make it no more than 2 states.
Technical Questions and Answers Product H8/300H Topic Disable Timing for Interrupts Q&A No. QA300H-015A Question Classification—H8/300H 1. Are interrupts disabled the instant that the peripheral module’s interrupt enable bit is cleared to 0? 2.
Technical Questions and Answers Product H8/300H Topic Exception Processing After a Reset Q&A No. QA300H-016A Question Classification—H8/300H Software Are interrupts ever generated immediately following resets? Registers Bus controller o Interrupts Resets Power-down mode Instructions Miscellaneous DMA controller ITU Watchdog timer SCI A/D converter I/O ports Related Manuals Answer No. Immediately after a reset, all interrupts, including NMIs, are disabled.
Technical Questions and Answers Product H8/300H Q&A No.
Technical Questions and Answers Product H8/300H Q&A No. Topic Using the Interrupt Controller QA300H-017A-2 Answer 1. 2. Procedure for setting interrupt priority: a. Set the UE (user bit enable) bit of the SYSCR (system control register) to 0, the I bit (interrupt mask) of the CCR (condition code register) to 1, and the CCR’s UI (user bit/interrupt mask) bit to 0. In this state, only NMIs and priority 1 interrupt sources are accepted. b.
Technical Questions and Answers Product H8/300H Q&A No. QA300H-018A Topic Receiving an External IRQ1 After Returning From Hardware Standby Mode Question Classification—H8/300H In the hardware standby mode, I set the IRQ1 pin to low and then left the hardware standby mode.
Technical Questions and Answers Product H8/300H Topic Interrupt Priority Within Groups Q&A No. QA300H-019A Question Classification—H8/300H 1. When external interrupts occur simultaneously within groups with the same priority (for example, IRQ4–IRQ7) which has priority? 2.
Technical Questions and Answers Product H8/300H Topic Interrupts When the Bus Is Released Q&A No. QA300H-020A Question Classification—H8/300H Software Are interrupts that occur when the bus is released held? Registers Bus controller o Interrupts Resets Power-down mode Instructions Miscellaneous DMA controller ITU Watchdog timer SCI A/D converter I/O ports Related Manuals Answer They are. After the bus release ends, they are accepted after the execution of one instruction.
Technical Questions and Answers Product H8/300H Q&A No.
Technical Questions and Answers Product H8/300H Topic Initializing SP After Reset Q&A No.
Technical Questions and Answers Product H8/300H Topic Pin State During Power-On Reset Q&A No.
Technical Questions and Answers Product H8/300H Topic RESO Pin Output From RES Pin Input Q&A No. QA300H-024A Question Classification—H8/300H Software What is the RESO pin state for reset state (RES = low)? Registers Bus controller Interrupts o Resets Power-down mode Instructions Miscellaneous DMA controller ITU Watchdog timer SCI A/D converter I/O ports Answer Related Manuals The RESO pin is high impedance for reset state (RES = low). It does not go to reset output (RESO = low).
Technical Questions and Answers Product H8/300H Q&A No. Topic Connecting RES and RESO Pins QA300H-025A Question Classification—H8/300H Software Is there any problem with taking RESO pin low output and inputting it directly to the RES pin? Registers Bus controller Interrupts o Resets Power-down mode Instructions Miscellaneous DMA controller ITU Watchdog timer SCI A/D converter I/O ports Answer Related Manuals Yes.
Technical Questions and Answers Product H8/300H Topic Cautions for Reset Input Q&A No.
Technical Questions and Answers Product H8/300H Q&A No.
Technical Questions and Answers Product H8/300H Q&A No. Topic Mode Pins During Hardware Standby Mode QA300H-028A Question Classification—H8/300H Software What happens when the mode pins (MD2–MD0) are changed in hardware standby mode? Registers Bus controller Interrupts Resets o Power-down mode Instructions Miscellaneous DMA controller ITU Watchdog timer SCI A/D converter I/O ports Related Manuals Answer The result is abnormal hardware standby mode operation.
Technical Questions and Answers Product H8/300H Q&A No.
Technical Questions and Answers Product H8/300H Q&A No. Topic Interrupt Sampling and Receiving in Sleep Mode QA300H-030A Question Classification—H8/300H 1. When are external interrupts sampled during sleep mode? 2. How many states after an interrupt is sampled is sleep mode cleared? Software Registers Bus controller Interrupts Resets o Power-down mode Instructions Miscellaneous DMA controller ITU Watchdog timer SCI A/D converter I/O ports Related Manuals Answer 1.
Technical Questions and Answers Product H8/300H Q&A No.
Technical Questions and Answers Product H8/300H Q&A No.
Technical Questions and Answers Product H8/300H Q&A No. QA300H-032A-2 Topic Operation When an Interrupt is Requested During Execution or While Fetching a SLEEP Instruction Answer NOP SLEEP instruction instruction Sleep mode φ Internal address bus 1 Internal data bus (16 bits) 2 3 4 Interrupt request signal (A) (B) (C) 1: SP 2: SP + 2 3: SLEEP instruction 4: Next instruction Note: During H8/3003 (mode 2, 2-state access) Figure 1.
Technical Questions and Answers Product H8/300H Q&A No. QA300H-033A Topic Support for the DAA (DAS) Instruction with the INC (DEC) Instruction Question 1. 2.
Technical Questions and Answers Product H8/300H Topic BRA and BRN Instructions Q&A No. QA300H-034A Question Classification—H8/300H 1. What is the difference between BRA (BT) and JMP? Also, what does it mean for the condition to be "True"? 2. What does it mean for the BRN (BF) condition to be "False"? Software Registers Bus controller Interrupts Resets Power-down mode o Instructions Miscellaneous DMA controller ITU Watchdog timer SCI A/D converter I/O ports Answer 1.
Technical Questions and Answers Product H8/300H Topic BRN Instruction Q&A No. QA300H-035A Question Classification—H8/300H Software What kind of instruction is BRN (BF)? Registers Bus controller Interrupts Resets Power-down mode o Instructions Miscellaneous DMA controller ITU Watchdog timer SCI A/D converter I/O ports Answer Related Manuals BRN is a convenient instruction that replaces conditional branch instructions during debugging.
Technical Questions and Answers Product H8/300H Q&A No.
Technical Questions and Answers Product H8/300H Q&A No. Topic Odd Address Values During STC Instruction Execution QA300H-037A Question Classification—H8/300H Software What is the odd address value when an STC instruction is executed and the CCR stored in an (register indirect) even address? Registers Bus controller Interrupts Resets Power-down mode o Instructions Miscellaneous DMA controller ITU Watchdog timer SCI A/D converter I/O ports Answer Related Manuals Manual Title Undefined.
Technical Questions and Answers Product H8/300H Q&A No. QA300H-038A Topic Interrupts and DMA Transfer Requests While the EEPMOV Instruction Is Executing Question Classification—H8/300H 1. When an interrupt occurs during the execution of an EEPMOV instruction, what happens to that interrupt request? 2.
Technical Questions and Answers Product H8/300H Q&A No. Topic The Difference Between EEPMOV.B and EEPMOV.W QA300H-039A Question Classification—H8/300H Software What is the difference between EEPMOV.B and EEPMOV.W? Registers Bus controller Interrupts Resets Power-down mode o Instructions Miscellaneous DMA controller ITU Watchdog timer SCI A/D converter I/O ports Answer Related Manuals The transfer data size of both the EEPMOV.B and EEPMOV.
Technical Questions and Answers Product H8/300H Topic Cautions on Stack Operation Q&A No. QA300H-040A Question Classification—H8/300H Software Are there any particular cautions about stack operation to be aware of? Registers Bus controller Interrupts Resets Power-down mode Instructions o Miscellaneous DMA controller ITU Watchdog timer SCI A/D converter I/O ports Related Manuals Answer On the H8/300H, the stack area is always accessed by word or longword.
Technical Questions and Answers Product H8/300H Q&A No. Topic On-Chip Peripheral LSI Access When the Bus Is Released QA300H-041A Question Classification—H8/300H Software Can external devices (bus master) access internal registers of the H8/300H when the H8/300H CPU has released the bus to an external device? Registers Bus controller Interrupts Resets Power-down mode Instructions o Miscellaneous DMA controller ITU Watchdog timer SCI A/D converter I/O ports Answer Related Manuals No.
Technical Questions and Answers Product H8/300H Q&A No. Topic Areas That Can Be Used as ROM by the Vector Table QA300H-042A Question Classification—H8/300H 1. Can the empty areas of the vector table (reserved by system or reserve) be used as ROM? 2. Can the empty areas of the I/O registers be used as ROM? Software Registers Bus controller Interrupts Resets Power-down mode Instructions o Miscellaneous DMA controller ITU Watchdog timer SCI A/D converter I/O ports Answer Related Manuals 1.
Technical Questions and Answers Product H8/300H Q&A No. Topic Pin State During the Oscillation Settling Time QA300H-043A Question Classification—H8/300H Software What are the pin states during oscillation settling time after the software standby mode is cleared? Registers Bus controller Interrupts Resets Power-down mode Instructions o Miscellaneous DMA controller ITU Watchdog timer SCI A/D converter I/O ports Answer Related Manuals Manual Title The same as in the software standby mode.
Section 2 On-Chip Peripherals Technical Questions and Answers Product Common Q&A No. Topic Receiving DMAC Startup Requests QA300H-101-1 Question Classification—H8/300H Software When a DMA controller startup request occurs: Registers Bus controller 1. When is the request forced to wait? 2. Is the request accepted under the following conditions? • During EEPMOV execution • During read-modify-write instruction execution • During DMAC cycle steal transfers.
Technical Questions and Answers Product Common Q&A No. Topic Receiving DMAC Startup Requests QA300H-101-2 Answer 2. During EEPMOV execution, requests are accepted between the read cycle and the write cycle. During read-modify-write instruction execution, requests are accepted between the read cycle, instruction fetch, and the write cycle. During cycle steal transfers, requests are accepted if the channel of the transfer request is higher in priority than the current channel. References 1.
Technical Questions and Answers Product Common Q&A No. Topic Addresses During DMA Transfers QA300H-102 Question Classification—H8/300H Software Doesn’t the CPU cause problems in DMAC operation if it reads the MAR (memory address register) during DMA transfers? Registers Bus controller Interrupts Resets Power-down mode Instructions Miscellaneous o DMA controller ITU Watchdog timer SCI A/D converter I/O ports Related Manuals Answer Reading the MAR does not have any affect on DMA operation.
Technical Questions and Answers Product Common Q&A No. Topic TEND Signal Output Timing 1 QA300H-103 Question Classification—H8/300H Software Is the TEND signal output at every byte/word transfer? Registers Bus controller Interrupts Resets Power-down mode Instructions Miscellaneous o DMA controller ITU Watchdog timer SCI A/D converter I/O ports Related Manuals Answer The TEND signal is output when the startup source is an external request (using the DREQ pin).
Technical Questions and Answers Product Common Q&A No. Topic TEND Signal Output Timing 2 QA300H-104 Question Classification—H8/300H Software At what timing is the TEND signal output? Registers Bus controller Interrupts Resets Power-down mode Instructions Miscellaneous o DMA controller ITU Watchdog timer SCI A/D converter I/O ports Related Manuals Answer The TEND signal is output in the write cycle when the ETCR (transfer count register) becomes H'00. Figure 2.4 illustrates the timing.
Technical Questions and Answers Product Common Q&A No. Topic The Relationship Between the DMAC’s DTE and DTIE Bits QA300H-105 Question Classification—H8/300H Software When the DTIE (data transfer interrupt enable) bit is 1 and the DTE (data transfer enable) bit is then cleared to 0, the manual says that an interrupt is requested of the CPU. Registers Bus controller Interrupts 1. 2. Will DMA transfer end interrupts occur continuously, as shown in figure 2.
Technical Questions and Answers Product Common Q&A No.
Technical Questions and Answers Product Common Topic The DMAC and Timer Interrupts Q&A No.
Technical Questions and Answers Product Common Q&A No. Topic Operation After a DMAC End Interrupt Is Generated 1 QA300H-108 Question Classification—H8/300H Software When the transfer count register becomes H'0000 while the DMAC is in use and an end interrupt is generated: 1. When is the next transfer request accepted? 2.
Technical Questions and Answers Product Common Q&A No.
Technical Questions and Answers Product Common Q&A No.
Technical Questions and Answers Product Common Q&A No. Topic Time Until DMAC Startup by the DREQ Pin QA300H-111 Question Classification—H8/300H Software Why is 4 states the minimum time to startup the DMAC from the DREQ pin? Registers Bus controller Interrupts Resets Power-down mode Instructions Miscellaneous o DMA controller ITU Watchdog timer SCI A/D converter I/O ports Answer Related Manuals The delay time from the DREQ pin to the internal DMAC module is 2 states.
Technical Questions and Answers Product Common Q&A No. Topic Reverse Operation in the DMA Repeat Mode QA300H-112 Question Classification—H8/300H Software What do I do to pause a DMA transfer that uses repeat mode and then start it up in the opposite direction? Registers Bus controller Interrupts Resets Power-down mode Instructions Miscellaneous o DMA controller ITU Watchdog timer SCI A/D converter I/O ports Related Manuals Answer Manual Title The flowchart in figure 2.
Technical Questions and Answers Product Common Topic Use of Dual-Function Pins Q&A No. QA300H-113 Question Classification—H8/300H Software When the DMAC is used under the following conditions, can the TEND/CS dual-function pin be used as a CS output? Registers Bus controller Conditions: Full-address transfer mode, external request (low level input from DREQ pin) for the startup source.
Technical Questions and Answers Product Common Topic I/O Ports and the DREQ Pin Q&A No. QA300H-114 Question 1. 2.
Technical Questions and Answers Product Common Q&A No.
Technical Questions and Answers Product Common Topic Clearing the Counters Q&A No. QA300H-116 Question Classification—H8/300H Software How do I clear the ITU counter using software? Registers Bus controller Interrupts Resets Power-down mode Instructions Miscellaneous DMA controller o ITU Watchdog timer SCI A/D converter I/O ports Answer Related Manuals Clear the TCNT (timer counter) by writing H'0000 to it. The counter value is not cleared by rewriting the TSTR (timer start register).
Technical Questions and Answers Product Common Topic Pulse Output From the ITU Q&A No. QA300H-117 Question Classification—H8/300H Software How do I get a specific number of pulses output (say, 10) and then stop the pulse output? Registers Bus controller Interrupts Resets Power-down mode Instructions Miscellaneous DMA controller o ITU Watchdog timer SCI A/D converter I/O ports Answer 1. 2. 3. Related Manuals When 1 DMAC channel can be used: Pulses are output in the ITU’s PWM mode.
Technical Questions and Answers Product Common Q&A No. Topic ITU Cascade Connections QA300H-118 Question Classification—H8/300H Software Can cascade connections be used with the ITU? Registers Bus controller Interrupts Resets Power-down mode Instructions Miscellaneous DMA controller o ITU Watchdog timer SCI A/D converter I/O ports Related Manuals Answer The PA2 and PA3 pins of port A are dual function pins for outputs TIOCA0 and TIOCB0 of the ITU’s channel 0 and clock inputs TCLKC and TCLKD.
Technical Questions and Answers Product Common Topic Setting the ITU’s PWM Output Q&A No. QA300H-119 Question Classification—H8/300H Software When the ITU is used in PWM mode, how should the TIOR (timer I/O control register) be set? Registers Bus controller Interrupts Resets Power-down mode Instructions Miscellaneous DMA controller o ITU Watchdog timer SCI A/D converter I/O ports Answer Related Manuals The TIOR setting does not affect PWM output.
Technical Questions and Answers Product Common Q&A No. Topic ITU Output and Port Output QA300H-120-1 Question Classification—H8/300H Software When the ITU is set to toggle output on a GRB (output capture/input compare dual-function register B) compare match to get the output shown in figure 2.
Technical Questions and Answers Product Common Q&A No. Topic ITU Output and Port Output QA300H-120-2 Answer 1. When port output is changed to ITU output, the value from before the change is output. 2. When a compare match signal is generated at the point when the port output is to be changed to ITU output, the value changes. (See figure 2.12.
Technical Questions and Answers Product Common Topic ITU Settings Q&A No. QA300H-121-1 Question Classification—H8/300H Software Please explain in detail the pulse width, cycle settings and register settings for ITU pulse output as well as the relationship to the internal clock.
Technical Questions and Answers Product Common Topic ITU Settings Q&A No. QA300H-121-2 Answer φ Internal clock (φ/4) 1.5 tcyc 1.5 tcyc H'0000 H'0000 TCNT H'0001 H'0000 TIOCA Figure 2.13 ITU Settings (1) φ Internal clock (φ/4) Compare match occurs n–1 n TCNT 0.5 tcyc n+1 n+1 n n–1 TIOCA Figure 2.14 ITU Settings (2) φ Internal clock (φ/4) Compare match occurs N–1 N 0.5 tcyc H'0000 TCNT N N–1 TIOCA Figure 2.
Technical Questions and Answers Product Common Topic ITU Settings Q&A No. QA300H-121-3 Answer Figure 2.15 TCNT value GRB (N) Figure 2.14 GRA (n) Time Figure 2.13 TIOCA output n N Figure 2.
Technical Questions and Answers Product Common Q&A No. QA300H-122 Topic Independent Operation of TCNT4 Using Reset-Synchronized PWM Mode Question Classification—H8/300H Software The manual states that "TCNT4 runs independently" when resetsynchronized PWM mode is used.
Technical Questions and Answers Product Common Topic Halting the WDT’s System Clock Q&A No.
Technical Questions and Answers Product Common Q&A No. Topic Using the RDR and TDR When the SCI Is Not Being Used QA300H-124 Question Classification—H8/300H Software When the SCI is not being used: Registers 1. Can the RDR (receive data register) be used as a data register? 2.
Technical Questions and Answers Product Common Topic I/O Settings of Clock Pins for the SCI Q&A No.
Technical Questions and Answers Product Common Topic Serial I/O Pin State Q&A No. QA300H-126 Question Classification—H8/300H Software After using the dual-function pins that can be used as I/O ports (TXD, RXD and SCK) as SCI pins, I reset them as I/O ports with the SCR (serial control register) and SMR (serial mode register).
Technical Questions and Answers Product Common Q&A No.
Technical Questions and Answers Product Common Topic RDRF Q&A No.
Technical Questions and Answers Product Common Topic Setting for Asynchronous Transmission Q&A No. QA300H-129-1 Question Classification—H8/300H Software Asynchronous transmission uses the SCI. How do I set it to do a transfer by software (i.e.
Technical Questions and Answers Product Common Q&A No. Topic Setting for Asynchronous Transmission QA300H-129-2 Answer (Empty interrupt generation) Rn ← Rn + 1 Rn = 16 No Yes TIE = 0 (interrupt disabled) (Rn)th byte of data is written to TDR; TDRE is cleared (TDRE is read and cleared) RTE Figure 2.
Technical Questions and Answers Product Common Q&A No. Topic How Data Is Transferred to the TDR QA300H-130-1 Question Classification—H8/300H Software Are there ways, when transferring transfer data located in 16-bit bus space to the SCI’s transmit data register (TDR, length 8 bits) as shown in figure 2.18, to: Registers Bus controller Interrupts 1. Transfer using software? 2.
Technical Questions and Answers Product Common Q&A No. Topic How Data Is Transferred to the TDR QA300H-130-2 Answer LOOP: MOV.B #12,R2L Waiting for interrupt DEC.B R2L Set the number of transfer words Can be placed in the sleep mode Copy the transfer data (1 byte) to R3L and increment the transfer buffer pointer (ER0) by 1 Continue until the transfer counter hits 0 TxI Interrupt: MOV.B @ER0+,R3L Transfer the transfer data to the SCI’s TDR MOV.
Technical Questions and Answers Product Common Q&A No. Topic Timing of Setting RDRF QA300H-131A-1 Question 1. Classification—H8/300H Software When data reception ends, the RDRF (receive data register full) flag of the SSR (serial status register) is set to 1. At what point in the asynchronous mode is the RDRF set? Registers Bus controller Interrupts 2.
Technical Questions and Answers Product Common Q&A No. Topic Timing of Setting RDRF QA300H-131A-2 Answer 2. The RDRF flag is set after the MSB data is received and synchronization clock rises. (See figure 2.22.) Synchronization clock Receive data Bit 6 Bit 7 RDRF Note: When SCK clock source is the internal clock, 1 state. When SCK clock source is the external clock, 2-3 states. Figure 2.
Technical Questions and Answers Product Common Q&A No. Topic Timing of Setting TDRE QA300H-132A-1 Question 1. Classification—H8/300H Software When 8-bit data transmission ends, the TDRE (transmit data register empty) flag of the SSR (serial status register) is set to 1. At what point in the asynchronous mode is the TDRE set? Registers Bus controller Interrupts 2.
Technical Questions and Answers Product Common Q&A No. Topic Timing of Setting TDRE QA300H-132A-2 Answer The start of transmission according to the setting of the TE (transmit enable) bit also follows this timing. (See figure 2.24.) T1 T2 T3 φ Internal write signal 9 10111213141516 1 2 3 4 5 6 7 8 9 10111213141516 1 2 3 4 5 6 7 8 9 10 11121314 Basic clock TDRE 2.5 states Figure 2.24 No transmit data in TSR (Asynchronous mode) 2. Clock-synchronous mode (See figures 2.25 and 2.26.
Technical Questions and Answers Product Common Topic SCI Reception Errors Q&A No.
Technical Questions and Answers Product Common Q&A No. Topic Operating the SCI in External Clock Mode QA300H-134 Question Classification—H8/300H Software When the SCI is operated in clock-synchronous external clock mode: 1. 2.
Technical Questions and Answers Product Common Topic System Clocks and SCK Phases Q&A No. QA300H-135 Question Classification—H8/300H Software Is the SCK (serial transfer clock) output synchronous to system clock (φ) rise or fall? Registers Bus controller Interrupts Resets Power-down mode Instructions Miscellaneous DMA controller ITU Watchdog timer o SCI A/D converter I/O ports Answer Related Manuals The SCK signal is output synchronous to system clock (φ) fall.
Technical Questions and Answers Product Common Q&A No. Topic Changing the A/D Mode and Channel During A/D Conversion QA300H-136 Question Classification—H8/300H 1. How do I switch the A/D conversion mode during A/D conversion? 2. How do I change the selected channel during A/D conversion? Software Registers Bus controller Interrupts Resets Power-down mode Instructions Miscellaneous DMA controller ITU Watchdog timer SCI o A/D converter I/O ports Related Manuals Answer 1.
Technical Questions and Answers Product Common Q&A No. Topic Using General-Purpose Ports QA300H-137 Question Classification—H8/300H Software Can instructions that manipulate bits be used on I/O ports when a bit of the port is designated an output port? Registers Bus controller Interrupts Resets Power-down mode Instructions Miscellaneous DMA controller ITU Watchdog timer SCI A/D converter o Answer I/O ports Related Manuals Yes.
Technical Questions and Answers Product Common Topic Processing Ports When Not in Use Q&A No. QA300H-138 Question Classification—H8/300H Software How should I process ports that are not in use? Registers Bus controller Interrupts Resets Power-down mode Instructions Miscellaneous DMA controller ITU Watchdog timer SCI A/D converter o Answer I/O ports Related Manuals 1.
