Product data

48
Answer
Product Common Q&A No. QA300H-101-2
Topic Receiving DMAC Startup Requests
2. During EEPMOV execution, requests are accepted between the read cycle and the write cycle.
During read-modify-write instruction execution, requests are accepted between the read cycle,
instruction fetch, and the write cycle. During cycle steal transfers, requests are accepted if the
channel of the transfer request is higher in priority than the current channel.
Technical Questions and Answers
References
1. BSET, BCLR, BNOT, BST and BIST are read-modify-write instructions.
2. When the wait is longer than those described above, wait states may have been inserted by a CPU bus
cycle that has a DREQ request. (See figure 2.1.)
Figure 2.1 Wait State Insertion
T1 T2 Tw T3 T1 T2 Tw T3
CPU cycle CPU cycle DMA cycle
DREQ
request
Requires 7 states
in the case shown