Product data

86
Answer
Product Common Q&A No. QA300H-132A-2
Topic Timing of Setting TDRE
The start of transmission according to the setting of the TE (transmit enable) bit also follows this timing.
(See figure 2.24.)
Figure 2.24 No transmit data in TSR (Asynchronous mode)
2. Clock-synchronous mode (See figures 2.25 and 2.26.)
Figure 2.25 Transmit data in TSR (Clock-synchronous mode)
Figure 2.26 No transmit data in TSR (Clock-synchronous mode)
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T1
φ
Internal
write signal
Basic clock
TDRE
T2 T3
2.5 states
Synchronization
clock
Transmit data
TDRE
Bit 6 Bit 7
When SCK clock source is the internal
clock, 2 state.
When SCK clock source is the external
clock, 1.5–2.5 state.
φ
Internal
write signal
TDRE
T1 T2 T3
2.5 states
TDRE set timing
Technical Questions and Answers