Product data

88
Classification—H8/300H
Software
Registers
Bus controller
Interrupts
Resets
Power-down mode
Instructions
Miscellaneous
DMA controller
ITU
Watchdog timer
o
SCI
A/D converter
I/O ports
Related Manuals
Manual Title
Other Technical
Documentation
Document Name
Related Microcomputer
Technical Q&A
Title
Question
References
Answer
Product Common Q&A No. QA300H-134
Topic Operating the SCI in External Clock Mode
When the SCI is operated in clock-synchronous external clock mode:
1. Does the SCI start the next transmit operation if, after the
completion of 1 byte of data transmission, the external clock is
applied to the SCK pin before the H8/300H CPU writes to the TDR
(transmit data register)?
2. What happens after reception?
The results are as follows:
1. Transmission does not start. The next transmission will not start
until the TDRE (transmit data register empty) of the SSR (serial
status register) is cleared to 0.
2. Reception starts, however, an overrun error will occur unless the
RDRF (receive data register full) of the SSR is cleared before the
next data is completely received.
Technical Questions and Answers