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ManualsBrandsRenesas ManualsComputer HardwareH8/300H Series

To our customers,

Old Company Name in Catalogs and Other Documents

On April 1

, 2010, NEC Electronics Corporation merged with Renesas Technology

Corporation, and Renesas

Electronics Corporation took over all the business of both

companies.

Therefore, although the old company name remains in this document, it is a valid

Renesas Electronics document. We appreciate your understanding.

Renesas Electronics website: http://www.renesas.com

April 1

, 2010

Renesas Electronics Corporation

Issued by: Renesas Electronics Corporation (http://www.renesas.com)

Send any inquiries to http://www.renesas.com/inquiry

Summary of content (277 pages)

PAGE 1
To our customers, Old Company Name in Catalogs and Other Documents On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the old company name remains in this document, it is a valid Renesas Electronics document. We appreciate your understanding. Renesas Electronics website: http://www.renesas.
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Notice 1. 2. 3. 4. 5. 6. 7. All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office.
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User’s Manual The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text. H8/300H Series 16 Software Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series Rev. 3.00 2004.
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Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage.
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General Precautions on Handling of Product 1. Treatment of NC Pins Note: Do not connect anything to the NC pins. The NC (not connected) pins are either not connected to any of the internal circuitry or are used as test pins or to reduce noise. If something is connected to the NC pins, the operation of the LSI is not guaranteed. 2. Treatment of Unused Input Pins Note: Fix all unused input pins to high or low level. Generally, the input pins of CMOS products are high-impedance input pins.
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Rev. 3.
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Preface The H8/300H Series is built around a 32-bit H8/300H CPU core with sixteen 16-bit registers, a concise, optimized instruction set designed for high-speed operation, and a 16-Mbyte linear address space. For easy migration from the H8/300 Series, the instruction set is upwardcompatible with the H8/300 Series at the object-code level. Programs coded in the high-level language C can be compiled to high-speed executable code.
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Rev. 3.
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Main Revisions for this Edition Item Page Revisions (See Manual for Details) All  All references to Hitachi, Hitachi, Ltd., Hitachi Semiconductors, and other Hitachi brand names changed to Renesas Technology Corp. Designation for categories changed from “series” to “group” Rev. 3.
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Rev. 3.
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Contents Section 1 1.1 1.2 1.3 1.4 1.5 1.6 CPU .................................................................................................................... Overview ........................................................................................................................... 1.1.1 Features ................................................................................................................ 1.1.2 Differences from H8/300 CPU..................................................
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2.2.4 (3) 2.2.5 2.2.6 2.2.7 2.2.8 2.2.9 2.2.10 2.2.11 2.2.12 2.2.13 2.2.14 2.2.15 2.2.16 2.2.17 2.2.18 2.2.19 2.2.20 2.2.21 2.2.22 (1) 2.2.22 (2) 2.2.22 (3) 2.2.23 2.2.24 2.2.25 (1) 2.2.25 (2) 2.2.25 (3) 2.2.26 (1) 2.2.26 (2) 2.2.26 (3) 2.2.27 (1) 2.2.27 (2) 2.2.28 (1) 2.2.28 (2) 2.2.29 (1) 2.2.29 (2) 2.2.30 (1) 2.2.30 (2) 2.2.31 (1) 2.2.31 (2) 2.2.31 (3) AND (L) .......................................................................................................... 49 ANDC...............................
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2.2.32 2.2.33 2.2.34 (1) 2.2.34 (2) 2.2.35 (1) 2.2.35 (2) 2.2.35 (3) 2.2.35 (4) 2.2.35 (5) 2.2.35 (6) 2.2.35 (7) 2.2.35 (8) 2.2.35 (9) 2.2.36 2.2.37 2.2.38 (1) 2.2.38 (2) 2.2.39 (1) 2.2.39 (2) 2.2.40 (1) 2.2.40 (2) 2.2.40 (3) 2.2.41 2.2.42 (1) 2.2.42 (2) 2.2.42 (3) 2.2.43 (1) 2.2.43 (2) 2.2.43 (3) 2.2.44 2.2.45 (1) 2.2.45 (2) 2.2.46 (1) 2.2.46 (2) 2.2.47 (1) 2.2.47 (2) 2.2.47 (3) 2.2.48 (1) 2.2.48 (2) 2.2.48 (3) JMP............................................................................................
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2.3 2.4 2.5 2.6 2.7 2.8 2.2.49 (1) ROTXL (B) ..................................................................................................... 155 2.2.49 (2) ROTXL (W) .................................................................................................... 156 2.2.49 (3) ROTXL (L)...................................................................................................... 157 2.2.50 (1) ROTXR (B) ......................................................................................
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Section 3 3.1 3.2 3.3 3.4 3.5 3.6 Processing States ............................................................................................ 245 Overview ........................................................................................................................... 245 Program Execution State ................................................................................................... 246 Exception-Handling State........................................................................
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Rev. 3.
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Section 1 CPU Section 1 CPU 1.1 Overview The H8/300H CPU is a high-speed central processing unit with an internal 32-bit architecture that is upward-compatible with the H8/300 CPU. The H8/300H CPU has sixteen 16-bit general registers, can address a 16-Mbyte linear address space, and is ideal for realtime control. 1.1.1 Features The H8/300H CPU has the following features.
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Section 1 CPU  16 ÷ 8-bit register-register divide: 875 ns  16 × 16-bit register-register multiply: 1375 ns  32 ÷ 16-bit register-register divide: 1375 ns • Two CPU operating modes  Normal mode  Advanced mode • Low-power mode  Transition to power-down state by SLEEP instruction 1.1.2 Differences from H8/300 CPU In comparison to the H8/300 CPU, the H8/300H CPU has the following enhancements. • More general registers Eight 16-bit registers have been added.
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Section 1 CPU 1.2 CPU Operating Modes The H8/300H CPU has two operating modes: normal and advanced. Normal mode supports a maximum 64-kbyte address space. Advanced mode supports up to 16 Mbytes. The mode is selected at the mode pins of the microcontroller. For further information, refer to the relevant hardware manual. Normal mode Maximum 64 kbytes, program and data areas combined Advanced mode Maximum 16 Mbytes, program and data areas combined CPU operating modes Figure 1.
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Section 1 CPU H'0000 H'0001 H'0002 H'0003 H'0004 H'0005 H'0006 H'0007 H'0008 H'0009 Reset exception vector Reserved for system use Exception vector table Exception vector 1 Exception vector 2 Figure 1.2 Exception Vector Table (normal mode) The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions uses an 8-bit absolute address to specify a memory operand that contains a branch address. In normal mode the operand is a 16-bit word operand, providing a 16-bit branch address.
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Section 1 CPU (2) Advanced Mode In advanced mode the exception vector table and stack structure differ from the H8/300 CPU. Address Space: Up to 16 Mbytes can be accessed linearly. Extended Registers (En): The extended registers (E0 to E7) can be used as 16-bit data registers, or they can be combined with the general registers (R0 to R7) for use as 32-bit data registers. When a 32-bit register is used as an address register, the upper 8 bits are ignored.
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Section 1 CPU The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions uses an 8-bit absolute address to specify a memory operand that contains a branch address. In advanced mode the operand is a 32-bit longword operand, of which the lower 24 bits are the branch address. Branch addresses can be stored in the top area from H'000000 to H'0000FF. Note that this area is also used for the exception vector table.
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Section 1 CPU 1.3 Address Space Figure 1.6 shows a memory map of the H8/300H CPU. (a) Normal mode H'0000 (b) Advanced mode H'000000 H'FFFF H'FFFFFF Figure 1.6 Memory Map Rev. 3.
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Section 1 CPU 1.4 Register Configuration 1.4.1 Overview The H8/300H CPU has the internal registers shown in figure 1.7. There are two types of registers: general and extended registers, and control registers.
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Section 1 CPU 1.4.2 General Registers The H8/300H CPU has eight 32-bit general registers. These general registers are all functionally alike and can be used without distinction between data registers and address registers. When a general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. When the general registers are used as 32-bit registers or as address registers, they are designated by the letters ER (ER0 to ER7).
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Section 1 CPU Free area SP (ER7) Stack area Figure 1.9 Stack 1.4.3 Control Registers The control registers are the 24-bit program counter (PC) and the 8-bit condition-code register (CCR). (1) Program Counter (PC) This 24-bit counter indicates the address of the next instruction the CPU will execute. The length of all CPU instructions is 16 bits (one word) or a multiple of 16 bits, so the least significant PC bit is ignored. When an instruction is fetched, the least significant PC bit is regarded as 0.
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Section 1 CPU Bit 5—Half-Carry Flag (H): When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B, or NEG.B instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 3, and cleared to 0 otherwise. When the ADD.W, SUB.W, CMP.W, or NEG.W instruction is executed, the H flag is set to 1 if there is a carry or borrow at bit 11, and cleared to 0 otherwise. When the ADD.L, SUB.L, CMP.L, or NEG.
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Section 1 CPU 1.5 Data Formats The H8/300H CPU can process 1-bit, 4-bit, 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, …, 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as two digits of 4-bit BCD data. 1.5.1 General Register Data Formats Figure 1.10 shows the data formats in general registers.
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Section 1 CPU Word data Rn Word data En 15 0 MSB 15 0 MSB Longword data LSB ERn 31 MSB LSB 16 15 En 0 Rn LSB Legend: ERn: General register ER En: General register E Rn: General register R RnH: General register RH RnL: General register RL MSB: Most significant bit LSB: Least significant bit Figure 1.10 General Register Data Formats (cont) Rev. 3.
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Section 1 CPU 1.5.2 Memory Data Formats Figure 1.11 shows the data formats on memory. The H8/300H CPU can access word data and longword data on memory, but word or longword data must begin at an even address. If an attempt is made to access word or longword data at an odd address, no address error occurs but the least significant bit of the address is regarded as 0, so the access starts at the preceding address. This also applies to instruction fetches.
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Section 1 CPU 1.6 Instruction Set 1.6.1 Overview The H8/300H CPU has 62 types of instructions, which are classified by function in table 1.1. For a detailed description of each instruction see section 2.2, Instruction Descriptions. Table 1.
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Section 1 CPU 1.6.2 Instructions and Addressing Modes Table 1.2 indicates the instructions available in the H8/300H CPU. Table 1.
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Section 1 CPU System control Block data transfer @aa:8 @aa:16 @aa:24 — — — — — — — JMP, JSR — — RTS — — — — — — — — — — — — — *2 — — — — — — @ERn+/@–ERn — @@aa:8 @(d:24,ERn) Bcc, BSR @(d:16,PC) @(d:16,ERn) — Instruction @(d:8,PC) @ERn Branch Rn Function #xx Addressing Modes — — — — TRAPA — — — — — — — — — — — — RTE — — — — — — — — — — — — SLEEP — — — — — — — — — — — — LDC B B W W W W — W W — — — — STC
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Section 1 CPU 1.6.3 Tables of Instructions Classified by Function Table 1.3 summarizes the instructions in each functional category. The notation used in table 1.3 is defined next.
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Section 1 CPU Table 1.3 Instructions Classified by Function Type Instruction Size* Function Data transfer MOV B/W/L (EAs) → Rd, Rs → (EAd) Moves data between two general registers or between a general register and memory, or moves immediate data to a general register. MOVFPE B (EAs) → Rd Moves external memory contents (addressed by @aa:16) to a general register in synchronization with an E clock.
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Section 1 CPU Type Instruction Size* Function Arithmetic operations ADDS L Rd ± 1 → Rd, Rd ± 2 → Rd, Rd ± 4 → Rd SUBS DAA Adds or subtracts the value 1, 2, or 4 to or from data in a 32-bit register. B DAS MULXS Rd decimal adjust → Rd Decimal-adjusts an addition or subtraction result in a general register by referring to the CCR to produce 4bit BCD data.
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Section 1 CPU Type Instruction Size* Function Arithmetic operations EXTS W/L Rd (sign extension) → Rd Extends byte data in the lower 8 bits of a 16-bit register to word data, or extends word data in the lower 16 bits of a 32-bit register to longword data, by extending the sign bit. EXTU W/L Rd (zero extension) → Rd Extends byte data in the lower 8 bits of a 16-bit register to word data, or extends word data in the lower 16 bits of a 32-bit register to longword data, by padding with zeros.
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Section 1 CPU Type Instruction Size* Function Bit-manipulation instructions BSET B 1 → ( of ) Sets a specified bit in a general register or memory operand to 1. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. BCLR B 0 → ( of ) Clears a specified bit in a general register or memory operand to 0. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. BNOT B ¬ (
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Section 1 CPU Type Instruction Size* Function Bit-manipulation instructions BOR B C ∨ ( of ) → C ORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. BIOR B C ∨ [¬ ( of )] → C ORs the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. The bit number is specified by 3-bit immediate data. BXOR B C ⊕ (
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Section 1 CPU Type Instruction Size* Function Branching instructions Bcc — Branches to a specified address if a specified condition is true. The branching conditions are listed below.
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Section 1 CPU Type Instruction Size* Function System control instructions TRAPA — Starts trap-instruction exception handling. RTE — Returns from an exception-handling routine. SLEEP — Causes a transition to the power-down state. LDC B/W (EAs) → CCR Moves the source operand contents to the condition code register. Byte transfer is performed in the #xx:8, Rs addressing mode and word transfer in other addressing modes. STC B/W CCR → (EAd) Transfers the CCR contents to a destination location.
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Section 1 CPU Type Instruction Size* Function Block data transfer instruction EEPMOV.B — if R4L ≠ 0 then Repeat @ER5 +→ @ER6 + R4L – 1→R4L Until R4L = 0 else next; EEPMOV.W — if R4 ≠ 0 then Repeat @ER5 +→ @ER6 + R4 – 1→R4L Until R4 = 0 else next; Transfers a data block according to parameters set in general registers R4L or R4, ER5, and R6.
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Section 1 CPU Condition Field: Specifies the branching condition of Bcc instructions. Figure 1.12 shows examples of instruction formats. (1) Operation field only op NOP, RTS, etc. (2) Operation field and register fields op rm rn ADD. Rn, Rm, etc. (3) Operation field, register fields, and effective address extension op rn rm EA (disp) MOV @(d:16, Rn), Rm (4) Operation field, effective address extension, and condition field op cc EA (disp) BRA @(d:8, PC) Figure 1.12 Instruction Formats Rev.
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Section 1 CPU 1.6.5 Addressing Modes and Effective Address Calculation (1) Addressing Modes The H8/300H CPU supports the eight addressing modes listed in table 1.4. Each instruction uses a subset of these addressing modes. Arithmetic and logic instructions can use the register direct and immediate modes. Data transfer instructions can use all addressing modes except program-counter relative and memory indirect.
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Section 1 CPU 4 Register Indirect with Post-Increment or Pre-Decrement—@ERn+ or @–ERn: • Register indirect with post-increment—@ERn+ The register field of the instruction code specifies an address register (ERn), the lower 24 bits of which contain the address of a memory operand. After the operand is accessed, 1, 2, or 4 is added to the address register contents (32 bits) and the sum is stored in the address register. The value added is 1 for byte access, 2 for word access, or 4 for longword access.
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Section 1 CPU 7 Program-Counter Relative—@(d:8, PC) or @(d:16, PC): This mode is used in the Bcc and BSR instructions. An 8-bit or 16-bit displacement contained in the instruction is sign-extended and added to the 24-bit program counter (PC) contents to generate a branch address.
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(4) (3) (2) (1) No. reg @ERn reg disp reg op reg • Register indirect with pre-decrement @–ERn op Register indirect with post-increment or pre-decrement • Register indirect with post-increment @ERn+ op Register indirect with displacement @(d:16, ERn) op Rn Regm Regn Register indirect op Register direct Addressing Mode and Instruction Format Table 1.
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Rev. 3.00 Dec 13, 2004 page 32 of 258 REJ09B0213-0300 (6) (5) No. op op abs abs op Immediate #xx:8/#xx:16/#xx:32 @aa:24 @aa:16 op @aa:8 Absolute address IMM abs Addressing Mode and Instruction Format Effective Address Calculation H'FFFF 23 8 7 Operand is immediate data.
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op abs abs General registers Operation field Displacement Absolute address Immediate data Advanced mode op Normal mode Memory indirect @@aa:8 op @(d:8, PC)/@(d:16, PC) Program-counter relative disp Addressing Mode and Instruction Format Legend: reg, regm, regn: op: disp: abs: IMM: (8) (7) No.
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Section 1 CPU Rev. 3.
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Section 2 Instruction Descriptions Section 2 Instruction Descriptions 2.1 Tables and Symbols This section explains how to read the tables describing each instruction. Note that the descriptions of some instructions extend over two pages or more. Mnemonic (full name): Gives the full and mnemonic names of the instruction. Type: Indicates the type of instruction. Operation: Describes the instruction in symbolic notation. (See section 2.1.2, Operation.
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Section 2 Instruction Descriptions 2.1.1 Assembler Format Example: ADD. B , Rd Destination operand Source operand Size Mnemonic The operand size is byte (B), word (W), or longword (L). Some instructions are restricted to a limited set of operand sizes. The symbol indicates that two or more addressing modes can be used. The H8/300H CPU supports the eight addressing modes listed next. Effective address calculation is described in section 1.7, Effective Address Calculation.
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Section 2 Instruction Descriptions 2.1.2 Operation The symbols used in the operation descriptions are defined as follows.
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Section 2 Instruction Descriptions 2.1.3 Condition Code Symbol Meaning ↔ The symbols used in the condition-code description are defined as follows. Changes according to the result of the instruction * Undetermined (no guaranteed value) 0 Always cleared to 0 — Not affected by execution of the instruction ∆ Varies depending on conditions; see the notes. 2.1.4 Instruction Format The symbols used in the instruction format descriptions are listed below.
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Section 2 Instruction Descriptions 2.1.5 Register Specification Address Register Specification: When a general register is used as an address register [@ERn, @(d:16, ERn), @(d:24, ERn), @ERn+, or @–ERn], the register is specified by a 3-bit register field (ers or erd). The lower 24 bits of the register are valid. Data Register Specification: A general register can be used as a 32-bit, 16-bit, or 8-bit data register, which is specified by a 3-bit register number.
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Section 2 Instruction Descriptions 2.1.6 Bit Data Access in Bit Manipulation Instructions Bit data is accessed as the n-th bit (n = 0, 1, 2, 3, …, 7) of a byte operand in a general register or memory. The bit number is given by 3-bit immediate data, or by the lower 3 bits of a general register value.
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Section 2 Instruction Descriptions 2.2 Instruction Descriptions The instructions are described starting in section 2.2.1. Rev. 3.
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Section 2 Instruction Descriptions 2.2.1 (1) ADD (B) ADD (ADD binary) Add Binary Operation U — N Z V C ↔ H ↔ UI — ↔ I — ↔ Rd + (EAs) → Rd ↔ Condition Code H: Set to 1 if there is a carry at bit 3; otherwise cleared to 0. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Set to 1 if an overflow occurs; otherwise cleared to 0. C: Set to 1 if there is a carry at bit 7; otherwise cleared to 0.
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Section 2 Instruction Descriptions 2.2.1 (2) ADD (W) ADD (ADD binary) Add Binary Operation U — N Z V C ↔ H ↔ UI — ↔ I — ↔ Rd + (EAs) → Rd ↔ Condition Code H: Set to 1 if there is a carry at bit 11; otherwise cleared to 0. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Set to 1 if an overflow occurs; otherwise cleared to 0. C: Set to 1 if there is a carry at bit 15; otherwise cleared to 0.
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Section 2 Instruction Descriptions 2.2.1 (3) ADD (L) ADD (ADD binary) Add Binary Operation U — N Z V C ↔ H ↔ UI — ↔ I — ↔ ERd + (EAs) → ERd ↔ Condition Code H: Set to 1 if there is a carry at bit 27; otherwise cleared to 0. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Set to 1 if an overflow occurs; otherwise cleared to 0. C: Set to 1 if there is a carry at bit 31; otherwise cleared to 0.
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Section 2 Instruction Descriptions 2.2.2 ADDS ADDS (ADD with Sign extension) Add Binary Address Data Operation Condition Code Rd + 1 → ERd Rd + 2 → ERd Rd + 4 → ERd I — H: N: Z: V: C: Assembly-Language Format ADDS #1, ERd ADDS #2, ERd ADDS #4, ERd UI — H — U — N — Z — V — C — Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged.
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Section 2 Instruction Descriptions 2.2.3 ADDX ADDX (ADD with eXtend carry) Add with Carry Operation U — N Z V C ↔ H ↔ UI — ↔ I — ↔ Rd + (EAs) + C → Rd ↔ Condition Code H: Set to 1 if there is a carry at bit 3; otherwise cleared to 0. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Previous value remains unchanged if the result is zero; otherwise cleared to 0. V: Set to 1 if an overflow occurs; otherwise cleared to 0.
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Section 2 Instruction Descriptions 2.2.4 (1) AND (B) AND (AND logical) Logical AND Operation Condition Code UI — H — U — N Z ↔ I — ↔ Rd ∧ (EAs) → Rd V 0 C — H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Always cleared to 0. C: Previous value remains unchanged. Assembly-Language Format AND.
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Section 2 Instruction Descriptions 2.2.4 (2) AND (W) AND (AND logical) Logical AND Operation Condition Code UI — H — U — N Z ↔ I — ↔ Rd ∧ (EAs) → Rd V 0 C — H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Always cleared to 0. C: Previous value remains unchanged. Assembly-Language Format AND.
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Section 2 Instruction Descriptions 2.2.4 (3) AND (L) AND (AND logical) Logical AND Operation I — UI — H — U — N Z ↔ ERd ∧ (EAs) → ERd ↔ Condition Code V 0 C — H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Always cleared to 0. C: Previous value remains unchanged. Assembly-Language Format AND.
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Section 2 Instruction Descriptions 2.2.5 ANDC ANDC (AND Control register) Logical AND with CCR Operation U N ↔ ↔ ↔ Z V C ↔ H ↔ UI ↔ I ↔ CCR ∧ #IMM → CCR ↔ Condition Code I: Stores the corresponding bit of the result. UI: Stores the corresponding bit of the result H: Stores the corresponding bit of the result. U: Stores the corresponding bit of the result N: Stores the corresponding bit of the result. Z: Stores the corresponding bit of the result.
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Section 2 Instruction Descriptions 2.2.6 BAND BAND (Bit AND) Bit Logical AND Condition Code C ∧ ( of ) → C I — UI — H — U — N — Z — V — C ↔ Operation Assembly-Language Format H: N: Z: V: C: BAND #xx:3, Operand Size Byte Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Stores the result of the operation.
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Section 2 Instruction Descriptions 2.2.7 Bcc Bcc (Branch conditionally) Conditional Branch Operation Condition Code If condition is true, then PC + disp → PC else next; I — H: N: Z: V: C: Assembly-Language Format Bcc disp → Condition field UI — H — U — N — Z — V — C — Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged.
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Section 2 Instruction Descriptions Bcc Bcc (Branch conditionally) Conditional Branch Operand Format and Number of States Required for Execution Addressing Mnemonic Mode Program-counter BRA (BT) relative Program-counter BRN (BF) relative Program-counter BHI relative Program-counter BLS relative Program-counter Bcc (BHS) relative Program-counter BCS (BLO) relative Program-counter BNE relative Program-counter BEQ relative Program-counter BVC relative Program-counter BVS relative Program-counter BPL relative
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Section 2 Instruction Descriptions 2.2.8 BCLR BCLR (Bit CLeaR) Bit Clear Operation Condition Code 0 → ( of ) I — Assembly-Language Format H: N: Z: V: C: BCLR #xx:3, BCLR Rn, Operand Size UI — H — U — N — Z — V — Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged.
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Section 2 Instruction Descriptions BCLR BCLR (Bit CLeaR) Bit Clear Operand Format and Number of States Required for Execution Addressing Mode* Mnemonic Operands Instruction Format 1st byte 2nd byte Register direct BCLR #xx:3, Rd 7 2 0 IMM rd Register indirect BCLR #xx:3, @ERd 7 D 0 erd 0 Absolute address BCLR #xx:3, @aa:8 7 F Register direct BCLR Rn, Rd 6 2 rn abs Register indirect BCLR Rn, @ERd 7 D 0 erd Absolute address BCLR Rn, @aa:8 7 F 3rd byte 4th byte 2
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Section 2 Instruction Descriptions 2.2.9 BIAND BIAND (Bit Invert AND) Bit Logical AND Condition Code C ∧ [¬ ( of )] → C I — UI — H — U — N — Z — V — C ↔ Operation Assembly-Language Format H: N: Z: V: C: BIAND #xx:3, Operand Size Byte Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Stores the result of the operation.
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Section 2 Instruction Descriptions 2.2.10 BILD BILD (Bit Invert LoaD) Bit Load Condition Code ¬ ( of ) → C I — Assembly-Language Format H: N: Z: V: C: BILD #xx:3, Operand Size Byte UI — H — U — N — Z — V — C ↔ Operation Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Loaded with the inverse of the specified bit.
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Section 2 Instruction Descriptions 2.2.11 BIOR BIOR (Bit Invert inclusive OR) Bit Logical OR Condition Code C ∨ [¬ ( of )] → C I — UI — H — U — N — Z — V — C ↔ Operation Assembly-Language Format H: N: Z: V: C: BIOR #xx:3, Operand Size Byte Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Stores the result of the operation.
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Section 2 Instruction Descriptions 2.2.12 BIST BIST (Bit Invert STore) Bit Store Condition Code Operation ¬ C → ( of ) I — UI — H — U — N — Z — V — C — Assembly-Language Format H: N: Z: V: C: BIST #xx:3, Operand Size Byte Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged.
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Section 2 Instruction Descriptions 2.2.13 BIXOR BIXOR (Bit Invert eXclusive OR) Bit Exclusive Logical OR Condition Code C ⊕ [¬ ( of )] → C I — UI — H — U — N — Z — V — C ↔ Operation Assembly-Language Format H: N: Z: V: C: BIXOR #xx:3, Operand Size Byte Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Stores the result of the operation.
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Section 2 Instruction Descriptions 2.2.14 BLD BLD (Bit LoaD) Bit Load Condition Code ( of ) → C I — UI — H — U — N — Z — V — C ↔ Operation Assembly-Language Format H: N: Z: V: C: BLD #xx:3, Operand Size Byte Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Loaded from the specified bit. Description This instruction loads a specified bit from the destination operand into the carry bit.
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Section 2 Instruction Descriptions 2.2.15 BNOT BNOT (Bit NOT) Bit NOT Operation Condition Code ¬ ( of ) → ( of ) I — Assembly-Language Format H: N: Z: V: C: BNOT #xx:3, BNOT Rn, Operand Size UI — H — U — N — Z — V — C — Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged.
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Section 2 Instruction Descriptions BNOT BNOT (Bit NOT) Bit NOT Operand Format and Number of States Required for Execution Addressing Mode* Mnemonic Operands Instruction Format 1st byte 2nd byte Register direct BNOT #xx:3, Rd 7 1 0 IMM rd Register indirect BNOT #xx:3, @ERd 7 D 0 erd 0 Absolute address BNOT #xx:3, @aa:8 7 F Register direct BNOT Rn, Rd 6 1 rn abs Register indirect BNOT Rn, @ERd 7 D 0 erd Absolute address BNOT Rn, @aa:8 7 F 3rd byte 4th byte 2 7 1
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Section 2 Instruction Descriptions 2.2.16 BOR BOR (bit inclusive OR) Bit Logical OR Condition Code C ∨ [( of )] → C I — UI — H — U — N — Z — V — C ↔ Operation Assembly-Language Format H: N: Z: V: C: BOR #xx:3, Operand Size Byte Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Stores the result of the operation.
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Section 2 Instruction Descriptions 2.2.17 BSET BSET (Bit SET) Bit Set Condition Code Operation 1 → ( of ) I — UI — H — U — N — Z — V — C — Assembly-Language Format H: N: Z: V: C: BSET #xx:3, BSET Rn, Operand Size Byte Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Description This instruction sets a specified bit in the destination operand to 1.
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Section 2 Instruction Descriptions BSET BSET (Bit SET) Bit Set Operand Format and Number of States Required for Execution Addressing Mode* Mnemonic Operands Instruction Format 1st byte 2nd byte Register direct BSET #xx:3, Rd 7 0 0 IMM rd Register indirect BSET #xx:3, @ERd 7 D 0 erd 0 Absolute address BSET #xx:3, @aa:8 7 F Register direct BSET Rn, Rd 6 0 rn abs Register indirect BSET Rn, @ERd 7 D 0 erd Absolute address BSET Rn, @aa:8 7 F 3rd byte 4th byte 2 7 0
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Section 2 Instruction Descriptions 2.2.18 BSR BSR (Branch to SubRoutine) Branch to Subroutine Operation Condition Code PC → @–SP PC + disp → PC I — Assembly-Language Format H: N: Z: V: C: BSR disp Operand Size UI — H — U — N — Z — V — C — Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. — Description This instruction branches to a subroutine at a specified address.
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Section 2 Instruction Descriptions BSR BSR (Branch to SubRoutine) Branch to Subroutine Notes The stack structure differs between normal mode and advanced mode. In normal mode only the lower 16 bits of the program counter are pushed on the stack. Reserved PC PC 23 16 15 87 0 23 Normal mode The branch address must be even. Rev. 3.
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Section 2 Instruction Descriptions 2.2.19 BST BST (Bit STore) Bit Store Condition Code Operation C → ( of ) I — UI — H — U — N — Z — V — C — Assembly-Language Format H: N: Z: V: C: BST #xx:3, Operand Size Byte Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged.
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Section 2 Instruction Descriptions 2.2.20 BTST BTST (Bit TeST) Bit Test Operation Condition Code I — Assembly-Language Format UI — H — U — N — Z ↔ ¬ ( of ) → Z V — C — H: Previous value remains unchanged. N: Previous value remains unchanged. Z: Set to 1 if the specified bit is zero; otherwise cleared to 0. V: Previous value remains unchanged. C: Previous value remains unchanged.
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Section 2 Instruction Descriptions BTST BTST (Bit TeST) Bit Test Operand Format and Number of States Required for Execution Addressing Mode* Mnemonic Operands Instruction Format 1st byte 2nd byte Register direct BTST #xx:3, Rd 7 3 0 IMM rd Register indirect BTST #xx:3, @ERd 7 C 0 erd 0 Absolute address BTST #xx:3, @aa:8 7 E Register direct BTST Rn, Rd 6 3 rn abs Register indirect BTST Rn, @ERd 7 C 0 erd Absolute address BTST Rn, @aa:8 7 E 3rd byte 4th byte 2 7
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Section 2 Instruction Descriptions 2.2.21 BXOR BXOR (Bit eXclusive OR) Bit Exclusive Logical OR Condition Code C ⊕ ( of ) → C I — UI — H — U — N — Z — V — C ↔ Operation Assembly-Language Format H: N: Z: V: C: BXOR #xx:3, Operand Size Byte Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Stores the result of the operation.
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Section 2 Instruction Descriptions 2.2.22 (1) CMP (B) CMP (CoMPare) Compare Operation U — N Z V C ↔ H ↔ UI — ↔ I — ↔ Rd – (EAs), set or clear CCR ↔ Condition Code H: Set to 1 if there is a borrow at bit 3; otherwise cleared to 0. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Set to 1 if an overflow occurs; otherwise cleared to 0. C: Set to 1 if there is a borrow at bit 7; otherwise cleared to 0.
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Section 2 Instruction Descriptions 2.2.22 (2) CMP (W) CMP (CoMPare) Compare Operation U — N Z V C ↔ H ↔ UI — ↔ I — ↔ Rd – (EAs), set CCR ↔ Condition Code H: Set to 1 if there is a borrow at bit 11; otherwise cleared to 0. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Set to 1 if an overflow occurs; otherwise cleared to 0. C: Set to 1 if there is a borrow at bit 15; otherwise cleared to 0.
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Section 2 Instruction Descriptions 2.2.22 (3) CMP (L) CMP (CoMPare) Compare Operation U — N Z V C ↔ H ↔ UI — ↔ I — ↔ ERd – (EAs), set CCR ↔ Condition Code I: Previous value remains unchanged. H: Set to 1 if there is a borrow at bit 27; otherwise cleared to 0. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Set to 1 if an overflow occurs; otherwise cleared to 0.
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Section 2 Instruction Descriptions 2.2.23 DAA DAA (Decimal Adjust Add) Decimal Adjust Operation UI — H * U — N Z V * C ↔ I — ↔ Rd (decimal adjust) → Rd ↔ Condition Code H: Undetermined (no guaranteed value). N: Set to 1 if the adjusted result is negative; otherwise cleared to 0. Z: Set to 1 if the adjusted result is zero; otherwise cleared to 0. V: Undetermined (no guaranteed value). C: Set to 1 if there is a carry at bit 7; otherwise left unchanged.
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Section 2 Instruction Descriptions DAA DAA (Decimal Adjust Add) Decimal Adjust Operand Format and Number of States Required for Execution Addressing Mode Register direct Mnemonic DAA Operands Rd Instruction Format 1st byte 2nd byte 0 0 F 3rd byte 4th byte rd No. of States 2 Notes Valid results (8-bit register Rd contents and C, V, Z, N, and H flags) are not assured if this instruction is executed under conditions other than those described above. Rev. 3.
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Section 2 Instruction Descriptions 2.2.24 DAS DAS (Decimal Adjust Subtract) Decimal Adjust Operation I — UI — H * U — N Z ↔ Rd (decimal adjust) → Rd ↔ Condition Code V * C — H: Undetermined (no guaranteed value). N: Set to 1 if the adjusted result is negative; otherwise cleared to 0. Z: Set to 1 if the adjusted result is zero; otherwise cleared to 0. V: Undetermined (no guaranteed value). C: Previous value remains unchanged.
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Section 2 Instruction Descriptions DAS DAS (Decimal Adjust Subtract) Decimal Adjust Operand Format and Number of States Required for Execution Addressing Mode Register direct Mnemonic Operands DAS Rd Instruction Format 1st byte 2nd byte 1 0 F 3rd byte 4th byte rd No. of States 2 Notes Valid results (8-bit register Rd contents and C, V, Z, N, and H flags) are not assured if this instruction is executed under conditions other than those described above. Rev. 3.
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Section 2 Instruction Descriptions 2.2.25 (1) DEC (B) DEC (DECrement) Decrement Operation UI — H U — — N Z V ↔ I — ↔ Rd – 1 → Rd ↔ Condition Code C — H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Set to 1 if an overflow occurs (the previous value in Rd was H'80); otherwise cleared to 0. C: Previous value remains unchanged. Assembly-Language Format DEC.
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Section 2 Instruction Descriptions 2.2.25 (2) DEC (W) DEC (DECrement) Decrement Operation UI — H U — — N Z V ↔ I — ↔ Rd – 1 → Rd Rd – 2 → Rd ↔ Condition Code C — H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Set to 1 if an overflow occurs (the previous value in Rd was H'8000); otherwise cleared to 0. C: Previous value remains unchanged. Assembly-Language Format DEC.
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Section 2 Instruction Descriptions 2.2.25 (3) DEC (L) DEC (DECrement) Decrement Operation UI — H U — — N Z V ↔ I — ↔ ERd – 1 → ERd ERd – 2 → ERd ↔ Condition Code C — H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Set to 1 if an overflow occurs; otherwise cleared to 0. C: Previous value remains unchanged. Assembly-Language Format DEC.L #1, ERd DEC.
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Section 2 Instruction Descriptions 2.2.26 (1) DIVXS (B) DIVXS (DIVide eXtend as Signed) Divide Signed Operation I — UI — H U — — N Z ↔ Rd ÷ Rs → Rd ↔ Condition Code V — C — H: Previous value remains unchanged. N: Set to 1 if the quotient is negative; otherwise cleared to 0. Z: Set to 1 if the divisor is zero; otherwise cleared to 0. V: Previous value remains unchanged. C: Previous value remains unchanged. Assembly-Language Format DIVXS.
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Section 2 Instruction Descriptions DIVXS (B) DIVXS (DIVide eXtend as Signed) Divide Signed Operand Format and Number of States Required for Execution Addressing Mode Register direct Mnemonic Operands DIVXS.B Rs, Rd Instruction Format 1st byte 2nd byte 3rd byte 4th byte 0 D 5 rs 1 0 1 rd No. of States 16 Notes The N flag is set to 1 if the dividend and divisor have different signs, and cleared to 0 if they have the same sign.
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Section 2 Instruction Descriptions 2.2.26 (2) DIVXS (W) DIVXS (DIVide eXtend as Signed) Divide Signed Operation I — UI — H U — — N Z ↔ ERd ÷ Rs → ERd ↔ Condition Code V — C — H: Previous value remains unchanged. N: Set to 1 if the quotient is negative; otherwise cleared to 0. Z: Set to 1 if the divisor is zero; otherwise cleared to 0. V: Previous value remains unchanged. C: Previous value remains unchanged. Assembly-Language Format DIVXS.
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Section 2 Instruction Descriptions DIVXS (W) DIVXS (DIVide eXtend as Signed) Divide Signed Operand Format and Number of States Required for Execution Addressing Mode Register direct Mnemonic Operands DIVXS.W Rs, ERd Instruction Format 1st byte 2nd byte 3rd byte 4th byte 0 D 5 rs 1 0 3 0 erd No. of States 24 Notes The N flag is set to 1 if the dividend and divisor have different signs, and cleared to 0 if they have the same sign.
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Section 2 Instruction Descriptions 2.2.26 (3) DIVXS DIVXS (DIVide eXtend as Signed) Divide Signed DIVXS instruction, Division by Zero, and Overflow Since the DIVXS instruction does not detect division by zero or overflow, applications should detect and handle division by zero and overflow using techniques similar to those used in the following program. 1. Programming solution for DIVXS.
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Section 2 Instruction Descriptions DIVXS DIVXS (DIVide eXtend as Signed) Divide Signed This program leaves a 16-bit quotient in R2 and an 8-bit remainder in R1H. R0L R1 R1H Divisor Dividend Remainder Quotient R2 Example 2: Sign extend the 8-bit divisor to 16 bits, sign extend the 16-bit dividend to 32 bits, and then use DIVXS to divide EXTS.W R0 BEQ ZERODIV EXTS.L ER1 DIVXS.
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Section 2 Instruction Descriptions DIVXS DIVXS (DIVide eXtend as Signed) Divide Signed 2. Programming solution for DIVXS.W R0, ER1 Example: Convert dividend and divisor to non-negative numbers, then use DIVXU programming solution for zero divide and overflow MOV.W BEQ ANDC BPL NEG.W ORC L1: MOV.L BPL NEG.L XORC L2: MOV.W EXTU.L DIVXU.W MOV.W DIVXU.W MOV.W MOV.W STC BTST BEQ NEG.W L3: BTST BEQ NEG.
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Section 2 Instruction Descriptions DIVXS DIVXS (DIVide eXtend as Signed) Divide Signed This program leaves a 32-bit quotient in ER2 and a 16-bit remainder in E1. Divisor R0 ER1 E1 Dividend Remainder Quotient ER2 The preceding two examples flag the status of the divisor and dividend in the UI and U bits in the CCR, and modify the sign of the quotient and remainder in the unsigned division result of the DIVXU instruction as shown next.
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Section 2 Instruction Descriptions 2.2.27 (1) DIVXU (B) DIVXU (DIVide eXtend as Unsigned) Divide Condition Code I — Assembly-Language Format UI — H U — — N Z ↔ Rd ÷ Rs → Rd ↔ Operation V — C — H: Previous value remains unchanged. N: Set to 1 if the divisor is negative; otherwise cleared to 0. Z: Set to 1 if the divisor is zero; otherwise cleared to 0. V: Previous value remains unchanged. C: Previous value remains unchanged. DIVXU.
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Section 2 Instruction Descriptions 2.2.27 (2) DIVXU (W) DIVXU (DIVide eXtend as Unsigned) Divide Operation Condition Code Assembly-Language Format UI — H U — — N Z ↔ I — ↔ ERd ÷ Rs → ERd V — C — H: Previous value remains unchanged. N: Set to 1 if the divisor is negative; otherwise cleared to 0. Z: Set to 1 if the divisor is zero; otherwise cleared to 0. V: Previous value remains unchanged. C: Previous value remains unchanged. DIVXU.
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Section 2 Instruction Descriptions DIVXU DIVXU (DIVide eXtend as Unsigned) Divide DIVXU Instruction, Zero Divide, and Overflow Zero divide and overflow are not detected in the DIVXU instruction. A program like the following can detect zero divisors and avoid overflow. 1. Programming solutions for DIVXU.B R0L, R1 Example 1: Divide upper 8 bits and lower 8 bits of 16-bit dividend separately and obtain 16-bit quotient CMP.
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Section 2 Instruction Descriptions DIVXU DIVXU (DIVide eXtend as Unsigned) Divide The resulting operation is 16 bits ÷ 8 bits → quotient (16 bits) and remainder (8 bits), and no overflow occurs. The 16-bit quotient is stored in R2, the 8-bit remainder in R1H. R0L R1 R2 Divisor Dividend Dividend (high) ( *1) R2 Remainder (part) Quotient (high) ( *2) R1 Remainder (part) Dividend (low) ( *3) R1 Remainder Quotient (low) ( *4) R1 Remainder Quotient (low) Sign extension R2 Rev. 3.
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Section 2 Instruction Descriptions DIVXU DIVXU (DIVide eXtend as Unsigned) Divide Example 2: Zero-extend divisor from 8 to 16 bits and dividend from 16 to 32 bits before dividing EXTU.W R0 ; Zero-extend 8-bit divisor to 16 bits BEQ ZERODIV ; Branch to ZERODIV if R0 = 0 EXTU.L ER1 ; Zero-extend 16-bit dividend to 32 bits EXTU.W R0, ER1 ; Divide using DIVXU.
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Section 2 Instruction Descriptions DIVXU DIVXU (DIVide eXtend as Unsigned) Divide 2. Programming solution for DIVXU.W R0, ER1 Example 1: Divide upper 16 bits and lower 16 bits of 32-bit dividend separately and obtain 32-bit quotient MOV.W R0, R0 ; R0 = 0? (Zero divisor?) BEQ ZERODIV ; Branch to ZERODIV if R0 = 0 MOV.W E1,E2 EXTU.L ER2 (*1) ; zero-extend to 32 bits DIVXU.W R0, ER2 (*2) ; Divide upper 16 bits of dividend MOV.W E2, E1 (*3) ; E2 → E1 (store partial remainder in E1) DIVXU.
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Section 2 Instruction Descriptions 2.2.28 (1) EEPMOV (B) EEPMOV (MOVe data to EEPROM) Block Data Transfer Operation Condition Code if R4L ≠ 0 then repeat I — @ER5+ → @ER6+ R4L – 1 → R4L until R4L = 0 else next; H: N: Z: V: C: Assembly-Language Format EEPMOV.B UI — H — U — N — Z — V — C — Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged.
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Section 2 Instruction Descriptions 2.2.28 (2) EEPMOV (W) EEPMOV (MOVe data to EEPROM) Block Data Transfer Operation Condition Code if R4 ≠ 0 then repeat I — @ER5+ → @ER6+ R4 – 1 → R4 until R4 = 0 else next; H: N: Z: V: C: Assembly-Language Format EEPMOV.W UI — H — U — N — Z — V — C — Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged.
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Section 2 Instruction Descriptions EEPMOV (W) EEPMOV (MOVe data to EEPROM) Block Data Transfer EEPMOV.W Instruction and NMI Interrupt If an NMI request occurs while the EEPMOV.W instruction is being executed, NMI interrupt exception handling is carried out at the end of the current read-write cycle.
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Section 2 Instruction Descriptions 2.2.29 (1) EXTS (W) EXTS (EXTend as Signed) Sign Extension Operation Condition Code UI — H U — — N Z ↔ I — ↔ ( of Rd) → ( of Rd> V 0 C — H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Always cleared to 0. C: Previous value remains unchanged. Assembly-Language Format EXTS.
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Section 2 Instruction Descriptions 2.2.29 (2) EXTS (L) EXTS (EXTend as Signed) Sign Extension Operation Condition Code UI — H U — — N Z ↔ I — ↔ ( of ERd) → ( of ERd>) V 0 C — I: Previous value remains unchanged. H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Always cleared to 0. C: Previous value remains unchanged. Assembly-Language Format EXTS.
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Section 2 Instruction Descriptions 2.2.30 (1) EXTU (W) EXTU (EXTend as Unsigned) Zero Extension Operation Condition Code I — Assembly-Language Format UI — H U — — N 0 Z ↔ 0 → ( of Rd>) Zero extend V 0 C — H: Previous value remains unchanged. N: Always cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Always cleared to 0. C: Previous value remains unchanged. EXTU.
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Section 2 Instruction Descriptions 2.2.30 (2) EXTU (L) EXTU (EXTend as Unsigned) Zero Extension Operation Condition Code I — Assembly-Language Format UI — H U — — N 0 Z ↔ 0 → ( of ERd>) Zero extend V 0 C — H: Previous value remains unchanged. N: Always cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Always cleared to 0. C: Previous value remains unchanged. EXTU.
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Section 2 Instruction Descriptions 2.2.31 (1) INC (B) INC (INCrement) Increment Operation UI — H U — — N Z V ↔ I — ↔ Rd + 1 → Rd ↔ Condition Code C — H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Set to 1 if an overflow occurs; otherwise cleared to 0. C: Previous value remains unchanged. Assembly-Language Format INC.
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Section 2 Instruction Descriptions 2.2.31 (2) INC (W) INC (INCrement) Increment Operation UI — H U — — N Z V ↔ I — ↔ Rd + 1 → Rd Rd + 2 → Rd ↔ Condition Code C — H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Set to 1 if an overflow occurs; otherwise cleared to 0. C: Previous value remains unchanged. Assembly-Language Format INC.W #1, Rd INC.
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Section 2 Instruction Descriptions 2.2.31 (3) INC (L) INC (INCrement) Increment Operation UI — H U — — N Z V ↔ I — ↔ ERd + 1 → ERd ERd + 2 → ERd ↔ Condition Code C — H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Set to 1 if an overflow occurs; otherwise cleared to 0. C: Previous value remains unchanged. Assembly-Language Format INC.L #1, ERd INC.
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Section 2 Instruction Descriptions 2.2.32 JMP JMP (JuMP) Unconditional Branch Operation Condition Code Effective address → PC I — Assembly-Language Format H: N: Z: V: C: JMP Operand Size UI — H — U — N — Z — V — C — Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged.
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Section 2 Instruction Descriptions 2.2.33 JSR JSR (Jump to SubRoutine) Jump to Subroutine Operation Condition Code PC → @–SP Effective address → PC I — Assembly-Language Format H: N: Z: V: C: JSR Operand Size UI — H — U — N — Z — V — C — Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged.
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Section 2 Instruction Descriptions JSR JSR (Jump to SubRoutine) Jump to Subroutine Notes Note that the structures of the stack and branch addresses differ between normal and advanced mode. Only the lower 16 bits of the PC are saved in normal mode. The branch address must be even. Reserved PC PC 23 16 15 87 0 23 Normal mode 16 15 87 0 Advanced mode Rev. 3.
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Section 2 Instruction Descriptions 2.2.34 (1) LDC (B) LDC (LoaD to Control register) Load CCR Operation H U N ↔ ↔ ↔ ↔ Z V C ↔ UI ↔ I ↔ (EAs) → CCR ↔ Condition Code I: Loaded from the corresponding bit in the source operand. H: Loaded from the corresponding bit in the source operand. N: Loaded from the corresponding bit in the source operand. Z: Loaded from the corresponding bit in the source operand. V: Loaded from the corresponding bit in the source operand.
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Section 2 Instruction Descriptions 2.2.34 (2) LDC (W) LDC (LoaD to Control register) Assembly-Language Format LDC.W , CCR Operand Size Word I UI H U N Z V C ↔ ↔ ↔ ↔ ↔ ↔ ↔ (EAs) → CCR Condition Code ↔ Operation Load CCR I: Loaded from the corresponding bit in the source operand. H: Loaded from the corresponding bit in the source operand. N: Loaded from the corresponding bit in the source operand. Z: Loaded from the corresponding bit in the source operand.
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Rev. 3.00 Dec 13, 2004 page 112 of 258 REJ09B0213-0300 Notes Absolute address Register indirect with post-increment Register indirect with displacement Register indirect Addressing Mode @aa:24,CCR @aa:16,CCR LDC.W LDC.W @ERs+,CCR LDC.W @(d:24,ERs),CCR 0 0 0 0 0 @(d:16,ERs),CCR LDC.W LDC.W 0 1 1 1 1 4 4 4 4 0 0 0 0 6 6 6 7 B B D 8 2 0 0 ers 0 ers 0 0 0 0 2 0 0 abs 0 disp 0 0 abs 10 8 8 12 8 0 0 ers F 6 0 4 No.
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Section 2 Instruction Descriptions 2.2.35 (1) MOV (B) MOV (MOVe data) Move Operation Condition Code UI — H U — — N Z ↔ I — ↔ Rs → Rd V 0 C — H: Previous value remains unchanged. N: Set to 1 if the data value is negative; otherwise cleared to 0. Z: Set to 1 if the data value is zero; otherwise cleared to 0. V: Always cleared to 0. C: Previous value remains unchanged. Assembly-Language Format MOV.
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Section 2 Instruction Descriptions 2.2.35 (2) MOV (W) MOV (MOVe data) Move Operation Condition Code UI — H U — — N Z ↔ I — ↔ Rs → Rd V 0 C — H: Previous value remains unchanged. N: Set to 1 if the data value is negative; otherwise cleared to 0. Z: Set to 1 if the data value is zero; otherwise cleared to 0. V: Always cleared to 0. C: Previous value remains unchanged. Assembly-Language Format MOV.
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Section 2 Instruction Descriptions 2.2.35 (3) MOV (L) MOV (MOVe data) Move Operation Condition Code UI — H U — — N Z ↔ I — ↔ ERs → ERd V 0 C — H: Previous value remains unchanged. N: Set to 1 if the data value is negative; otherwise cleared to 0. Z: Set to 1 if the data value is zero; otherwise cleared to 0. V: Always cleared to 0. C: Previous value remains unchanged. Assembly-Language Format MOV.
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Section 2 Instruction Descriptions 2.2.35 (4) MOV (B) MOV (MOVe data) Assembly-Language Format MOV.B , Rd Operand Size Byte I — UI — H U — — N Z ↔ (EAs) → Rd Condition Code ↔ Operation Move V 0 C — H: Previous value remains unchanged. N: Set to 1 if the data value is negative; otherwise cleared to 0. Z: Set to 1 if the data value is zero; otherwise cleared to 0. V: Always cleared to 0. C: Previous value remains unchanged.
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MOV.B @aa:24,Rd @aa:16,Rd @aa:8,Rd MOV.B MOV.B @ERs+,Rd MOV.B @(d:24,ERs),Rd 6 6 2 6 A A rd C 8 2 0 abs 0 ers 0 ers rd rd rd 0 rd 0 ers E 6 7 rd 0 ers IMM 8 rd 2nd byte 6 F 1st byte 0 6 0 A abs disp 2 rd 4th byte Instruction Format 3rd byte 0 abs 0 5th byte 6th byte disp 7th byte 8th byte 8 6 4 6 10 6 4 2 No. of States For the @aa:8 access range, refer to the relevant microcontroller hardware manual. Notes The MOV.
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Section 2 Instruction Descriptions 2.2.35 (5) MOV (W) MOV (MOVe data) Assembly-Language Format MOV.W , Rd Operand Size Word I — UI — H U — — N Z ↔ (EAs) → Rd Condition Code ↔ Operation Move V 0 C — H: Previous value remains unchanged. N: Set to 1 if the data value is negative; otherwise cleared to 0. Z: Set to 1 if the data value is zero; otherwise cleared to 0. V: Always cleared to 0. C: Previous value remains unchanged.
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@aa:24,Rd @aa:16,Rd MOV.W MOV.W @ERs+,Rd MOV.W @(d:24,ERs),Rd 6 6 6 B B D 8 2 0 0 ers 0 ers 0 ers F 6 7 0 ers 0 9 9 B 2 rd 0 abs 0 disp 8th byte 4 No. of States rd rd rd 0 0 0 abs 8 6 6 10 6 6 7th byte rd 6th byte 4 disp 5th byte Instruction Format 4th byte IMM 3rd byte rd rd 2nd byte 6 7 1st byte Notes 1. The source operand must be located at an even address. 2. In machine language, MOV.W @R7+, Rd is identical to POP.W Rd.
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Section 2 Instruction Descriptions 2.2.35 (6) MOV (L) MOV (MOVe data) Move Operation I — UI — H U — — N Z ↔ (EAs) → ERd ↔ Condition Code V 0 C — H: Previous value remains unchanged. N: Set to 1 if the data value is negative; otherwise cleared to 0. Z: Set to 1 if the data value is zero; otherwise cleared to 0. V: Always cleared to 0. C: Previous value remains unchanged. Assembly-Language Format MOV.
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@aa:24,ERd 0 1 0 0 0 0 1 0 @aa:16,ERd MOV.L MOV.L 0 0 0 1 0 0 1 @ERs+,ERd 0 MOV.L @(d:24,ERs),ERd 6 6 6 7 B B D 8 F 9 0 2 0 0 erd 0 erd 0 ers 0 erd 0 ers 0 ers 0 erd 0 ers 0 erd 0 6 0 B abs disp 2 0 erd 6th byte Instruction Format 5th byte IMM 4th byte Notes 1. The source operand must be located at an even address. 2. In machine language, MOV.L @ER7+, ERd is identical to POP.L ERd. Absolute address Register indirect with post-increment MOV.
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Section 2 Instruction Descriptions 2.2.35 (7) MOV (B) MOV (MOVe data) Assembly-Language Format MOV.B Rs, Operand Size Byte I — UI — H U — — N Z ↔ Rs → (EAd) Condition Code ↔ Operation Move V 0 C — H: Previous value remains unchanged. N: Set to 1 if the data value is negative; otherwise cleared to 0. Z: Set to 1 if the data value is zero; otherwise cleared to 0. V: Always cleared to 0. C: Previous value remains unchanged.
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6 6 Rs,@aa:24 MOV.B 3 Rs,@aa:16 Rs,@aa:8 MOV.B 6 7 6 6 A A rs C A 8 abs 1 erd 0 erd rs rs rs 0 rs 1 erd E 8 rs 1 erd 2nd byte 8 1st byte MOV.B Rs,@–ERd MOV.B Rs,@(d:24,ERd) Rs,@(d:16,ERd) MOV.B MOV.B Rs,@ERd Operands MOV.B Mnemonic 0 6 0 A abs disp A rs 4th byte Instruction Format 3rd byte 0 abs 0 5th byte 6th byte disp 7th byte 8th byte 8 6 4 6 10 6 4 No. of States 1. The MOV.
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Section 2 Instruction Descriptions 2.2.35 (8) MOV (W) MOV (MOVe data) Assembly-Language Format MOV.W Rs, Operand Size Word I — UI — H U — — N Z ↔ Rs → (EAd) Condition Code ↔ Operation Move V 0 C — H: Previous value remains unchanged. N: Set to 1 if the data value is negative; otherwise cleared to 0. Z: Set to 1 if the data value is zero; otherwise cleared to 0. V: Always cleared to 0. C: Previous value remains unchanged.
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Rs,@aa:24 Rs,@aa:16 MOV.W MOV.W Rs,@–ERd MOV.W Rs,@(d:24,ERd) Rs,@(d:16,ERd) MOV.W MOV.W Rs,@ERd Operands MOV.W Mnemonic 6 6 6 7 6 6 B B D A 8 1 erd 0 erd rs rs rs 0 rs 1 erd F 8 rs 1 erd 2nd byte 9 1st byte 0 6 0 B abs disp A rs 4th byte Instruction Format 3rd byte 0 abs 0 5th byte 6th byte disp 7th byte 8th byte 8 6 6 10 6 4 No. of States Notes 1. The destination operand must be located at an even address. 2. In machine language, MOV.
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Section 2 Instruction Descriptions 2.2.35 (9) MOV (L) MOV (MOVe data) Move Operation I — UI — H U — — N Z ↔ ERs → (EAd) ↔ Condition Code V 0 C — H: Previous value remains unchanged. N: Set to 1 if the data value is negative; otherwise cleared to 0. Z: Set to 1 if the data value is zero; otherwise cleared to 0. V: Always cleared to 0. C: Previous value remains unchanged. Assembly-Language Format MOV.
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ERs,@aa:24 ERs,@aa:16 MOV.L MOV.L ERs,@–ERd MOV.L ERs,@(d:24,ERd) ERs,@(d:16,ERd) MOV.L MOV.L ERs,@ERd Operands MOV.L Mnemonic 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 6 6 6 7 B B D 8 0 A 8 0 ers 0 ers 1 erd 0 ers 1 erd A 0 ers 0 abs 0 disp 0 0 abs 12 10 10 14 10 1 erd 0 ers F 6 0 0 1 No.
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Section 2 Instruction Descriptions 2.2.36 MOVFPE MOVFPE (MOVe From Peripheral with E clock) Move Data with E Clock Condition Code I — Assembly-Language Format UI — H U — — N Z ↔ (EAs) → Rd Synchronized with E clock ↔ Operation V 0 C — H: Previous value remains unchanged. N: Set to 1 if the data value is negative; otherwise cleared to 0. Z: Set to 1 if the data value is zero; otherwise cleared to 0. V: Always cleared to 0. C: Previous value remains unchanged.
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Section 2 Instruction Descriptions 2.2.37 MOVTPE MOVTPE (MOVe To Peripheral with E clock) Operation Move Data with E Clock Condition Code Assembly-Language Format UI — H U — — N Z ↔ I — ↔ Rs → (EAd) Synchronized with E clock V 0 C — H: Previous value remains unchanged. N: Set to 1 if the data value is negative; otherwise cleared to 0. Z: Set to 1 if the data value is zero; otherwise cleared to 0. V: Always cleared to 0. C: Previous value remains unchanged.
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Section 2 Instruction Descriptions 2.2.38 (1) MULXS (B) MULXS (MULtiply eXtend as Signed) Multiply Signed I — Assembly-Language Format UI — H — U — N Z ↔ Rd × Rs → Rd ↔ Condition Code Operation V — C — H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Previous value remains unchanged. C: Previous value remains unchanged. MULXS.
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Section 2 Instruction Descriptions 2.2.38 (2) MULXS (W) MULXS (MULtiply eXtend as Signed) Multiply Signed I — Assembly-Language Format UI — H — U — N Z ↔ ERd × Rs → ERd ↔ Condition Code Operation V — C — H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Previous value remains unchanged. C: Previous value remains unchanged. MULXS.
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Section 2 Instruction Descriptions 2.2.39 (1) MULXU (B) MULXU (MULtiply eXtend as Unsigned) Multiply Operation Condition Code Rd × Rs → Rd I — Assembly-Language Format H: N: Z: V: C: MULXU.B Rs, Rd Operand Size Byte UI — H — U — N — Z — V — C — Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged.
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Section 2 Instruction Descriptions 2.2.39 (2) MULXU (W) MULXU (MULtiply eXtend as Unsigned) Multiply Operation Condition Code ERd × Rs → ERd I — Assembly-Language Format H: N: Z: V: C: MULXU.W Rs, ERd Operand Size Word UI — H — U — N — Z — V — C — Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged.
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Section 2 Instruction Descriptions 2.2.40 (1) NEG (B) NEG (NEGate) Negate Binary Signed Operation U — N Z V C ↔ H ↔ UI — ↔ I — ↔ 0 – Rd → Rd ↔ Condition Code H: Set to 1 if there is a borrow at bit 3; otherwise cleared to 0. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Set to 1 if an overflow occurs; otherwise cleared to 0. C: Set to 1 if there is a borrow at bit 7; otherwise cleared to 0.
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Section 2 Instruction Descriptions 2.2.40 (2) NEG (W) NEG (NEGate) Negate Binary Signed Operation U — N Z V C ↔ H ↔ UI — ↔ I — ↔ 0 – Rd → Rd ↔ Condition Code H: Set to 1 if there is a borrow at bit 11; otherwise cleared to 0. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Set to 1 if an overflow occurs; otherwise cleared to 0. C: Set to 1 if there is a borrow at bit 15; otherwise cleared to 0.
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Section 2 Instruction Descriptions 2.2.40 (3) NEG (L) NEG (NEGate) Negate Binary Signed Operation U — N Z V C ↔ H ↔ UI — ↔ I — ↔ 0 – ERd → ERd ↔ Condition Code H: Set to 1 if there is a borrow at bit 27; otherwise cleared to 0. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Set to 1 if an overflow occurs; otherwise cleared to 0. C: Set to 1 if there is a borrow at bit 31; otherwise cleared to 0.
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Section 2 Instruction Descriptions 2.2.41 NOP NOP (No OPeration) No Operation Operation Condition Code PC + 2 → PC I — Assembly-Language Format H: N: Z: V: C: NOP Operand Size UI — H — U — N — Z — V — C — Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. — Description This instruction only increments the program counter, causing the next instruction to be executed.
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Section 2 Instruction Descriptions 2.2.42 (1) NOT (B) NOT (NOT = logical complement) Logical Complement Operation Condition Code UI — H U — — N Z ↔ I — ↔ ¬ Rd → Rd V 0 C — H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Always cleared to 0. C: Previous value remains unchanged. Assembly-Language Format NOT.
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Section 2 Instruction Descriptions 2.2.42 (2) NOT (W) NOT (NOT = logical complement) Logical Complement Operation Condition Code UI — H U — — N Z ↔ I — ↔ ¬ Rd → Rd V 0 C — H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero (the previous Rd value was H'FFFF); otherwise cleared to 0. V: Always cleared to 0. C: Previous value remains unchanged. Assembly-Language Format NOT.
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Section 2 Instruction Descriptions 2.2.42 (3) NOT (L) NOT (NOT = logical complement) Logical Complement Operation Condition Code UI — H U — — N Z ↔ I — ↔ ¬ ERd → ERd V 0 C — I: Previous value remains unchanged. H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Always cleared to 0. C: Previous value remains unchanged. Assembly-Language Format NOT.
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Section 2 Instruction Descriptions 2.2.43 (1) OR (B) OR (inclusive OR logical) Logical OR Operation Condition Code UI — H U — — N Z ↔ I — ↔ Rd ∨ (EAs) → Rd V 0 C — H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Always cleared to 0. C: Previous value remains unchanged. Assembly-Language Format OR.
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Section 2 Instruction Descriptions 2.2.43 (2) OR (W) OR (inclusive OR logical) Logical OR Operation Condition Code UI — H U — — N Z ↔ I — ↔ Rd ∨ (EAs) → Rd V 0 C — H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Always cleared to 0. C: Previous value remains unchanged. Assembly-Language Format OR.
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Section 2 Instruction Descriptions 2.2.43 (3) OR (L) OR (inclusive OR logical) Logical OR Operation I — UI — H U — — N Z ↔ ERd ∨ (EAs) → ERd ↔ Condition Code V 0 C — H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Always cleared to 0. C: Previous value remains unchanged. Assembly-Language Format OR.
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Section 2 Instruction Descriptions 2.2.44 ORC ORC (inclusive OR Control register) Logical OR with CCR Operation U N ↔ ↔ ↔ Z V C ↔ H ↔ UI ↔ I ↔ CCR ∨ #IMM → CCR ↔ Condition Code I: Stores the corresponding bit of the result. UI: Stores the corresponding bit of the result. H: Stores the corresponding bit of the result. U: Stores the corresponding bit of the result. N: Stores the corresponding bit of the result. Z: Stores the corresponding bit of the result.
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Section 2 Instruction Descriptions 2.2.45 (1) POP (W) POP (POP data) Pop Data from Stack Operation Condition Code UI — H U — — N Z ↔ I — ↔ @SP+ → Rn V 0 C — H: Previous value remains unchanged. N: Set to 1 if the data value is negative; otherwise cleared to 0. Z: Set to 1 if the data value is zero; otherwise cleared to 0. V: Always cleared to 0. C: Previous value remains unchanged. Assembly-Language Format POP.
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Section 2 Instruction Descriptions 2.2.45 (2) POP (L) POP (POP data) Pop Data from Stack Operation Condition Code UI — H U — — N Z ↔ I — ↔ @SP+ → ERn V 0 C — H: Previous value remains unchanged. N: Set to 1 if the data value is negative; otherwise cleared to 0. Z: Set to 1 if the data value is zero; otherwise cleared to 0. V: Always cleared to 0. C: Previous value remains unchanged. Assembly-Language Format POP.
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Section 2 Instruction Descriptions 2.2.46 (1) PUSH (W) PUSH (PUSH data) Push Data on Stack Operation Condition Code UI — H U — — N Z ↔ I — ↔ Rn → @–SP V 0 C — H: Previous value remains unchanged. N: Set to 1 if the data value is negative; otherwise cleared to 0. Z: Set to 1 if the data value is zero; otherwise cleared to 0. V: Always cleared to 0. C: Previous value remains unchanged. Assembly-Language Format PUSH.
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Section 2 Instruction Descriptions 2.2.46 (2) PUSH (L) PUSH (PUSH data) Push Data on Stack Operation Condition Code UI — H U — — N Z ↔ I — ↔ ERn → @–SP V 0 C — H: Previous value remains unchanged. N: Set to 1 if the data value is negative; otherwise cleared to 0. Z: Set to 1 if the data value is zero; otherwise cleared to 0. V: Always cleared to 0. C: Previous value remains unchanged. Assembly-Language Format PUSH.
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Section 2 Instruction Descriptions 2.2.47 (1) ROTL (B) ROTL (ROTate Left) Rotate Operation Condition Code H U — — N Z V 0 C ↔ UI — ↔ I — ↔ Rd (left rotation) → Rd H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Always cleared to 0. C: Receives the previous value in bit 7. Assembly-Language Format ROTL.
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Section 2 Instruction Descriptions 2.2.47 (2) ROTL (W) ROTL (ROTate Left) Rotate Operation Condition Code H U — — N Z V 0 C ↔ UI — ↔ I — ↔ Rd (left rotation) → Rd H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Always cleared to 0. C: Receives the previous value in bit 15. Assembly-Language Format ROTL.
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Section 2 Instruction Descriptions 2.2.47 (3) ROTL (L) ROTL (ROTate Left) Rotate Operation Condition Code UI — H U — — N Z ↔ I — ↔ ERd (left rotation) → ERd V 0 C — H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Always cleared to 0. C: Receives the previous value in bit 31. Assembly-Language Format ROTL.
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Section 2 Instruction Descriptions 2.2.48 (1) ROTR (B) ROTR (ROTate Right) Rotate Operation Condition Code H U — — N Z V 0 C ↔ UI — ↔ I — ↔ Rd (right rotation) → Rd H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Always cleared to 0. C: Receives the previous value in bit 0. Assembly-Language Format ROTR.
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Section 2 Instruction Descriptions 2.2.48 (2) ROTR (W) ROTR (ROTate Right) Rotate Operation Condition Code H U — — N Z V 0 C ↔ UI — ↔ I — ↔ Rd (right rotation) → Rd H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Always cleared to 0. C: Receives the previous value in bit 0. Assembly-Language Format ROTR.
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Section 2 Instruction Descriptions 2.2.48 (3) ROTR (L) ROTR (ROTate Right) Rotate Operation Condition Code H U — — N Z V 0 C ↔ UI — ↔ I — ↔ ERd (right rotation) → ERd H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Always cleared to 0. C: Receives the previous value in bit 0. Assembly-Language Format ROTR.
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Section 2 Instruction Descriptions 2.2.49 (1) ROTXL (B) ROTXL (ROTate with eXtend carry Left) Rotate through Carry Operation Condition Code H U — — N Z V 0 C ↔ UI — ↔ I — ↔ Rd (left rotation through carry bit) → Rd H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Always cleared to 0. C: Receives the previous value in bit 7. Assembly-Language Format ROTXL.
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Section 2 Instruction Descriptions 2.2.49 (2) ROTXL (W) ROTXL (ROTate with eXtend carry Left) Rotate through Carry Operation Condition Code H U — — N Z V 0 C ↔ UI — ↔ I — ↔ Rd (left rotation through carry bit) → Rd H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Always cleared to 0. C: Receives the previous value in bit 15. Assembly-Language Format ROTXL.
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Section 2 Instruction Descriptions 2.2.49 (3) ROTXL (L) ROTXL (ROTate with eXtend carry Left) Rotate through Carry Operation Condition Code H U — — N Z V 0 C ↔ UI — ↔ I — ↔ ERd (left rotation through carry bit) → ERd H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Always cleared to 0. C: Receives the previous value in bit 31. Assembly-Language Format ROTXL.
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Section 2 Instruction Descriptions 2.2.50 (1) ROTXR (B) ROTXR (ROTate with eXtend carry Right) Rotate through Carry Operation Condition Code H U — — N Z V 0 C ↔ UI — ↔ I — ↔ Rd (right rotation through carry bit) → Rd H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Always cleared to 0. C: Receives the previous value in bit 0. Assembly-Language Format ROTXR.
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Section 2 Instruction Descriptions 2.2.50 (2) ROTXR (W) ROTXR (ROTate with eXtend carry Right) Rotate through Carry Operation Condition Code H U — — N Z V 0 C ↔ UI — ↔ I — ↔ Rd (right rotation through carry bit) → Rd H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Always cleared to 0. C: Receives the previous value in bit 0. Assembly-Language Format ROTXR.
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Section 2 Instruction Descriptions 2.2.50 (3) ROTXR (L) ROTXR (ROTate with eXtend carry Right) Rotate through Carry Operation Condition Code H U — — N Z V 0 C ↔ UI — ↔ I — ↔ ERd (right rotation through carry bit) → ERd H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Always cleared to 0. C: Receives the previous value in bit 0. Assembly-Language Format ROTXR.
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Section 2 Instruction Descriptions 2.2.51 RTE RTE (ReTurn from Exception) Return from Exception Handling Operation U N ↔ ↔ ↔ Z V C ↔ H ↔ UI ↔ I ↔ @SP+ → CCR @SP+ → PC ↔ Condition Code I: Restored from the corresponding bit on the stack. UI: Restored from the corresponding bit on the stack. H: Restored from the corresponding bit on the stack. U: Restored from the corresponding bit on the stack. N: Restored from the corresponding bit on the stack.
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Section 2 Instruction Descriptions RTE RTE (ReTurn from Exception) Return from Exception Handling Notes The stack structure differs between normal mode and advanced mode. Don’t care PC Normal mode CCR CCR 23 Undet. 16 15 PC 87 Rev. 3.
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Section 2 Instruction Descriptions 2.2.52 RTS RTS (ReTurn from Subroutine) Return from Subroutine Condition Code Operation @SP+ → PC I — UI — H — U — N — Z — V — C — Assembly-Language Format H: N: Z: V: C: RTS Operand Size — Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged.
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Section 2 Instruction Descriptions 2.2.53 (1) SHAL (B) SHAL (SHift Arithmetic Left) Shift Arithmetic Operation H — U — N Z V C ↔ UI — ↔ I — ↔ Rd (left arithmetic shift) → Rd ↔ Condition Code H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Set to 1 if an overflow occurs; otherwise cleared to 0. C: Receives the previous value in bit 7. Assembly-Language Format SHAL.
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Section 2 Instruction Descriptions 2.2.53 (2) SHAL (W) SHAL (SHift Arithmetic Left) Shift Arithmetic Operation Assembly-Language Format H — U — N Z V C ↔ UI — ↔ I — ↔ Rd (left arithmetic shift) → Rd ↔ Condition Code H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Set to 1 if an overflow occurs; otherwise cleared to 0. C: Receives the previous value in bit 15. SHAL.
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Section 2 Instruction Descriptions 2.2.53 (3) SHAL (L) SHAL (SHift Arithmetic Left) Shift Arithmetic Operation H — U — N Z V C ↔ UI — ↔ I — ↔ ERd (left arithmetic shift) → ERd ↔ Condition Code H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Set to 1 if an overflow occurs; otherwise cleared to 0. C: Receives the previous value in bit 31. Assembly-Language Format SHAL.
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Section 2 Instruction Descriptions 2.2.54 (1) SHAR (B) SHAR (SHift Arithmetic Right) Shift Arithmetic Operation Condition Code H U — — N Z V 0 C ↔ UI — ↔ I — ↔ Rd (right arithmetic shift) → Rd H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Set to 1 if an overflow occurs; otherwise cleared to 0. C: Receives the previous value in bit 0. Assembly-Language Format SHAR.
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Section 2 Instruction Descriptions 2.2.54 (2) SHAR (W) SHAR (SHift Arithmetic Right) Shift Arithmetic Operation Condition Code UI — H U — — N Z ↔ I — ↔ Rd (right arithmetic shift) → Rd V 0 C — H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Set to 1 if an overflow occurs; otherwise cleared to 0. C: Receives the previous value in bit 0. Assembly-Language Format SHAR.
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Section 2 Instruction Descriptions 2.2.54 (3) SHAR (L) SHAR (SHift Arithmetic Right) Shift Arithmetic Operation Condition Code H U — — N Z V 0 C ↔ UI — ↔ I — ↔ ERd (right arithmetic shift) → ERd H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Set to 1 if an overflow occurs; otherwise cleared to 0. C: Receives the previous value in bit 0. Assembly-Language Format SHAR.
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Section 2 Instruction Descriptions 2.2.55 (1) SHLL (B) SHLL (SHift Logical Left) Shift Logical Condition Code I — Assembly-Language Format UI — H U — — N Z ↔ Rd (left logical shift) → Rd ↔ Operation V 0 C — H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Always cleared to 0. C: Receives the previous value in bit 7. SHLL.
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Section 2 Instruction Descriptions 2.2.55 (2) SHLL (W) SHLL (SHift Logical Left) Shift Logical Condition Code Assembly-Language Format UI — H U — — N Z V 0 C ↔ I — ↔ Rd (left logical shift) → Rd ↔ Operation H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Always cleared to 0. C: Receives the previous value in bit 15. SHLL.
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Section 2 Instruction Descriptions 2.2.55 (3) SHLL (L) SHLL (SHift Logical Left) Shift Logical Condition Code Assembly-Language Format UI — H U — — N Z V 0 C ↔ I — ↔ ERd (left logical shift) → ERd ↔ Operation H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Always cleared to 0. C: Receives the previous value in bit 31. SHLL.
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Section 2 Instruction Descriptions 2.2.56 (1) SHLR (B) SHLR (SHift Logical Right) Shift Logical Operation Condition Code UI — H U — — N 0 Z V 0 C ↔ I — ↔ Rd (right logical shift) → Rd H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Always cleared to 0. C: Receives the previous value in bit 0. Assembly-Language Format SHLR.
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Section 2 Instruction Descriptions 2.2.56 (2) SHLR (W) SHLR (SHift Logical Right) Shift Logical Operation Condition Code Assembly-Language Format UI — H U — — N 0 Z V 0 C ↔ I — ↔ Rd (right logical shift) → Rd H: Previous value remains unchanged. N: Always cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Always cleared to 0. C: Receives the previous value in bit 0. SHLR.
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Section 2 Instruction Descriptions 2.2.56 (3) SHLR (L) SHLR (SHift Logical Right) Shift Logical Operation Condition Code Assembly-Language Format UI — H U — — N 0 Z V 0 C ↔ I — ↔ ERd (right logical shift) → ERd H: Previous value remains unchanged. N: Always cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Always cleared to 0. C: Receives the previous value in bit 0. SHLR.
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Section 2 Instruction Descriptions 2.2.57 SLEEP SLEEP (SLEEP) Power-Down Mode Operation Condition Code Program execution state → power-down mode I — Assembly-Language Format H: N: Z: V: C: SLEEP Operand Size — UI — H — U — N — Z — V — C — Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged.
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Section 2 Instruction Descriptions 2.2.58 (1) STC (B) STC (STore from Control register) Store CCR Operation Condition Code CCR → Rd I — Assembly-Language Format H: N: Z: V: C: STC.B CCR, Rd Operand Size UI — H — U — N — Z — V — C — Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Byte Description This instruction copies the CCR contents to an 8-bit register Rd.
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Section 2 Instruction Descriptions 2.2.58 (2) STC (W) STC (STore from Control register) Operation Store CCR Condition Code CCR → (EAd) Assembly-Language Format STC.W CCR, Operand Size I — H: N: Z: V: C: UI — H — U — N — Z — V — C — Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Word Description This instruction copies the CCR contents to a destination location.
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Notes Absolute address Register indirect with pre-decrement Register indirect with displacement Register indirect Addressing Mode CCR,@aa:24 CCR,@aa:16 STC.W STC.W CCR,@–ERd STC.W CCR,@(d:24,ERd) 0 0 0 0 0 CCR,@(d:16,ERd) STC.W STC.W 0 1 1 1 1 4 4 4 4 0 0 0 0 6 6 6 7 B B D 8 A 8 1 erd 0 erd 0 0 0 0 A 0 0 abs 0 disp 0 0 abs 10 8 8 12 8 0 1 erd F 6 0 4 No.
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Section 2 Instruction Descriptions 2.2.59 (1) SUB (B) SUB (SUBtract binary) Subtract Binary Operation Assembly-Language Format U — N Z V C ↔ H ↔ UI — ↔ I — ↔ Rd – Rs → Rd ↔ Condition Code H: Set to 1 if there is a borrow at bit 3; otherwise cleared to 0. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Set to 1 if an overflow occurs; otherwise cleared to 0.
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Section 2 Instruction Descriptions SUB (B) SUB (SUBtract binary) Subtract Binary Notes The SUB.B instruction can operate only on general registers. Immediate data can be subtracted from general register contents by using the SUBX instruction. Before executing SUBX #xx:8, Rd, first set the Z flag to 1 and clear the C flag to 0. The following coding examples can also be used to subtract nonzero immediate data #IMM. (1) ORC #H'05, CCR SUBX #(IMM–1), Rd (2) ADD #(0–IMM), Rd XORC #H'01, CCR Rev. 3.
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Section 2 Instruction Descriptions 2.2.59 (2) SUB (W) SUB (SUBtract binary) Subtract Binary Operation Assembly-Language Format U — N Z V C ↔ H ↔ UI — ↔ I — ↔ Rd – (EAs) → Rd ↔ Condition Code H: Set to 1 if there is a borrow at bit 11; otherwise cleared to 0. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Set to 1 if an overflow occurs; otherwise cleared to 0.
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Section 2 Instruction Descriptions 2.2.59 (3) SUB (L) SUB (SUBtract binary) Subtract Binary Operation Assembly-Language Format U — N Z V C ↔ H ↔ UI — ↔ I — ↔ ERd – → ERd ↔ Condition Code H: Set to 1 if there is a borrow at bit 27; otherwise cleared to 0. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Set to 1 if an overflow occurs; otherwise cleared to 0.
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Section 2 Instruction Descriptions 2.2.60 SUBS SUBS (SUBtract with Sign extension) Subtract Binary Address Data Operation Condition Code ERd – 1 → ERd ERd – 2 → ERd ERd – 4 → ERd I — H: N: Z: V: C: Assembly-Language Format SUBS #1, ERd SUBS #2, ERd SUBS #4, ERd UI — H — U — N — Z — V — C — Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged.
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Section 2 Instruction Descriptions 2.2.61 SUBX SUBX (SUBtract with eXtend carry) Subtract with Borrow Operation U — N Z V C ↔ H ↔ UI — ↔ I — ↔ Rd – (EAs) – C → Rd ↔ Condition Code H: Set to 1 if there is a borrow from bit 3; otherwise cleared to 0. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Set to 1 if an overflow occurs; otherwise cleared to 0.
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Section 2 Instruction Descriptions 2.2.62 TRAPA TRAPA (TRAP Always) Trap Unconditionally Operation Condition Code PC → @–SP CCR → @–SP → PC I 1 I: U: H: N: Z: V: C: Assembly-Language Format TRAPA #x:2 Operand Size — UI H ∆*1 — U — N — Z — V — C — Always set to 1. See notes. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged.
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Section 2 Instruction Descriptions 2.2.63 (1) XOR (B) XOR (eXclusive OR logical) Exclusive Logical OR Operation Condition Code UI — H U — — N Z ↔ I — ↔ Rd ⊕ (EAs) → Rd V 0 C — H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Always cleared to 0. C: Previous value remains unchanged. Assembly-Language Format XOR.
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Section 2 Instruction Descriptions 2.2.63 (2) XOR (W) XOR (eXclusive OR logical) Exclusive Logical OR Operation Condition Code UI — H U — — N Z ↔ I — ↔ Rd ⊕ (EAs) → Rd V 0 C — H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Always cleared to 0. C: Previous value remains unchanged. Assembly-Language Format XOR.
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Section 2 Instruction Descriptions 2.2.63 (3) XOR (L) XOR (eXclusive OR logical) Exclusive Logical OR Operation I — UI — H U — — N Z ↔ ERd ⊕ (EAs) → ERd ↔ Condition Code V 0 C — H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Always cleared to 0. C: Previous value remains unchanged. Assembly-Language Format XOR.
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Section 2 Instruction Descriptions 2.2.64 XORC XORC (eXclusive OR Control register) Exclusive Logical OR with CCR Operation U N ↔ ↔ ↔ Z V C ↔ H ↔ UI ↔ I ↔ CCR ⊕ #IMM → CCR ↔ Condition Code I: Stores the corresponding bit of the result. UI: Stores the corresponding bit of the result. H: Stores the corresponding bit of the result. U: Stores the corresponding bit of the result. N: Stores the corresponding bit of the result. Z: Stores the corresponding bit of the result.
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Section 2 Instruction Descriptions 2.3 Instruction Set Summary Table 2.
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Section 2 Instruction Descriptions @aa:8 @aa:16 @aa:24 — — — — — — — — @ERn+/@–ERn — @@aa:8 @(d:24,ERn) Bcc, BSR @(d:16,PC) @(d:16,ERn) — Instruction @(d:8,PC) @ERn Branch Rn Function #xx Addressing Modes — — JMP, JSR — — — — — — — — — RTS — — — — — — — — — — — — TRAPA, RTE, SLEEP — — — — — — — — — — — — LDC B B W W W W — W W — — — — STC — B W W W W — W W — — — — ANDC, ORC, XORC B — — — — — — — — — — —
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Section 2 Instruction Descriptions Table 2.2 Instruction Set (1) Data Transfer Instructions Addressing Mode and Instruction Length (bytes) B MOV.B @ERs,Rd B 2 2 AdH N Z V C Normal vanced #xx:8→Rd8 — — Rs8→Rd8 — — @ERs→Rd8 — — MOV.B @(d:16, ERs), Rd B 4 @(d:16,ERs)→Rd8 — — MOV.B @(d:24,ERs),Rd B 8 @(d24:,ERs24)→Rd8 — — MOV.B @ERs+,Rd B @ERs→Rd8,ERs32+1→ERs32 — — MOV.B @aa:8,Rd B 2 @aa:8→Rd8 — — MOV.B @aa:16,Rd B 4 @aa:16→Rd8 — — MOV.
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Section 2 Instruction Descriptions Condition Code 0 — 0 — MOVFPE MOVFPE@aa:16,Rd B 4 @aa:16→Rd (synchronized with E clock) — — MOVTPE MOVTPE Rs,@aa:16 B 4 Rs→@aa:16 (synchronized with E clock)R — — 0 — MOV POP PUSH MOV.L @(d:16,ERs),ERd L 6 @(d:16,ERs)→ERd32 — — MOV.L @(d:24,ERs),ERd L 10 @(d:24,ERs)→ERd32 — — ERs→ERd32,ERs32+4→@ERs32 — — 4 MOV.L @ERs+,ERd L MOV.L @aa:16,ERd L 6 @aa:16→ERd32 — — MOV.L @aa:24,ERd L 8 @aa:24→ERd32 — — MOV.
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Section 2 Instruction Descriptions (2) Arithmetic Operation Instructions Addressing Mode and Instruction Length (bytes) Size #xx Rn @ERn @(d,ERn) @ERn+/@–ERn @aa @(d,PC) @@aa — ↔ ↔ ↔ ↔ ↔ 2 ↔ ↔ ↔ ↔ ↔ 2 ADD.W #xx:16,Rd W 4 ↔ ↔ ↔ ↔ 4 ADD.W Rs,Rd W ↔ ↔ ↔ ↔ 2 ADD.L #xx:32,ERd L 6 ↔ ↔ ↔ ↔ 6 ADD.L ERs,ERd L ADDX #xx:8,Rd B 2 ADDX Rs,Rd B 2 Rd8+Rs8+C→Rd8 — ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ 2 ADDS.L #1,ERd L 2 ERd32+1→ERd32 — — — — — — 2 2 ADDS.
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Section 2 Instruction Descriptions Addressing Mode and Instruction Length (bytes) EXTU EXTS ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ 2 ↔ ↔ ↔ ↔ ↔ 2 ↔ ↔ ↔ ↔ ↔ 2 ↔ ↔ ↔ ↔ 4 ↔ ↔ ↔ ↔ 2 ↔ ↔ ↔ ↔ DIVXS 2 4 ↔ ↔ ↔ ↔ DIVXU 2 2 2 — — — — — — 14 14 Rd16 × Rs16→ERd32 (unsigned operation) — — — — — — 22 22 4 Rd8 × Rs8 → Rd16 (signed operation) — — — — 16 16 W 4 Rd16 × Rs16 → ERd32 (signed operation) — — — — 24 24 DIVXU.
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Section 2 Instruction Descriptions (3) Logic Operation Instructions Addressing Mode and Instruction Length (bytes) XOR NOT B 2 B I AdH N Z V C Normal vanced Rd8 ∧ #xx:8→Rd8 — — 2 Rd8 ∧ Rs8→Rd8 — — Rd16 ∧ #xx:16→Rd16 — — 2 Rd16 ∧ Rs16→Rd16 — — ERd32 ∧ #xx:32→ERd32 — — ERd32 ∧ ERs32→ERd32 — — Rd8 ∨ #xx:8→Rd8 — — Rd8 ∨ Rs8→Rd8 — — Rd16 ∨ #xx:16→Rd16 — — Rd16 ∨ Rs16→Rd16 — — ERd32 ∨ #xx:32→ERd32 — — ERd32 ∨ ERs32→ERd32 — — Rd8⊕#xx:8→Rd8 — — Rd8⊕Rs8→Rd8 — — Rd16⊕#xx:16→Rd16
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Section 2 Instruction Descriptions (4) Shift Instructions Addressing Mode and Instruction Length (bytes) SHAL.L ERd L SHAR.B Rd B 2 — — 2 — — SHAR.W Rd W 2 — — SHAR.L ERd L 2 SHLL.B Rd B 2 SHLL.W Rd W 2 SHLL.L ERd L 2 — — SHLR.B Rd B 2 — — SHLR.W Rd W 2 SHLR.L ERd L 2 — — ROTXL.B Rd B 2 — — ROTXL.W Rd W 2 — — ROTXL.L ERd L 2 ROTXR.B Rd B 2 — — ROTXR.W Rd W 2 — — ROTXR.L ERd L 2 ROTL.B Rd B 2 ROTL.W Rd W 2 ROTL.L ERd L 2 ROTR.
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Section 2 Instruction Descriptions (5) Bit Manipulation Instructions BNOT BTST BLD BILD B B BSET #xx:3,@aa:8 B BSET Rn,Rd B BSET Rn,@ERd B BSET Rn,@aa:8 B BCLR #xx:3,Rd B BCLR #xx:3,@ERd B BCLR #xx:3,@aa:8 B BCLR Rn,Rd B BCLR Rn,@ERd B BCLR Rn,@aa:8 B BNOT #xx:3,Rd B BNOT #xx:3,@ERd B BNOT #xx:3,@aa:8 B BNOT Rn,Rd B BNOT Rn,@ERd B BNOT Rn,@aa:8 B BTST #xx:3,Rd B BTST #xx:3,@ERd B BTST #xx:3,@aa:8 B BTST Rn,Rd B BTST Rn,@ERd B BTST Rn,@aa:8 B BLD #xx:3,Rd B
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Section 2 Instruction Descriptions BAND BIAND BOR BIOR BXOR BIXOR B B BST #xx:3,@aa:8 B BIST #xx:3,Rd B BIST #xx:3,@ERd B BIST #xx:3,@aa:8 B BAND #xx:3,Rd B BAND #xx:3,@ERd B BAND #xx:3,@aa:8 B BIAND #xx:3,Rd B BIAND #xx:3,@ERd B BIAND #xx:3,@aa:8 B BOR #xx:3,Rd B BOR #xx:3,@ERd B BOR #xx:3,@aa:8 B BIOR #xx:3,Rd B BIOR #xx:3,@ERd B BIOR #xx:3,@aa:8 B BXOR #xx:3,Rd B BXOR #xx:3,@ERd B BXOR #xx:3,@aa:8 B BIXOR #xx:3,Rd B BIXOR #xx:3,@ERd B BIXOR #xx:3,@aa:8 B
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Section 2 Instruction Descriptions (6) Branch Instructions Mnemonic Bcc Size #xx Rn @ERn @(d,ERn) @ERn+/@–ERn @aa @(d,PC) @@aa — Addressing Mode and Instruction Length (bytes) BRA d:8(BTd:8) — 2 BRA d:16(BTd:16) — 4 BRN d:8(BFd:8) — 2 BRN d:16(BFd:16) — 4 BHI d:8 — 2 BHI d:16 — 4 BLS d:8 — 2 BLS d:16 — 4 BCC d:8(BHS d:8) — 2 BCC d:16(BHS d:16) — 4 BCS d:8(BLO d:8) — 2 BCS d:16(BLO d:16) — 4 BNE d:8 — 2 BNE d:16 — 4 BEQ d:8 — 2 BEQ d:16 — 4 BVC d:8 — 2
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Section 2 Instruction Descriptions Mnemonic JMP BSR JSR RTS Size #xx Rn @ERn @(d,ERn) @ERn+/@–ERn @aa @(d,PC) @@aa — Addressing Mode and Instruction Length (bytes) JMP @ERn — JMP @aa:24 — JMP @@aa:8 — BSR d:8 — BSR d:16 — JSR @ERn — JSR @aa:24 — JSR @@aa:8 — RTS — 2 Condition Code Operation Branch condition I No.
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Section 2 Instruction Descriptions (7) System Control Instructions Addressing Mode and Instruction Length (bytes) Size #xx Rn @ERn @(d,ERn) @ERn+/@–ERn @aa @(d,PC) @@aa — LDC #xx:8,CCR B 2 LDC Rs,CCR B LDC @ERs,CCR W LDC @(d:16,ERs),CCR W LDC @(d:16,ERs),CCR W LDC @ERs+,CCR W LDC @aa:16,CCR W 6 LDC @aa:24,CCR W 8 STC CCR,@(d:16,ERs) W STC CCR,@(d:24,ERs) W 10 10 Transition to power-down state — — — — — — 2 2 #xx:8→CCR 2 Rs8→CCR 2 @ERs→CCR 6 6 @(d:16,ERs)→CCR 10 @(d:24,
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Section 2 Instruction Descriptions (8) Block Transfer Instructions Mnemonic Size #xx Rn @ERn @(d,ERn) @ERn+/@–ERn @aa @(d,PC) @@aa — Addressing Mode and Instruction Length (bytes) Condition Code Operation I No. of States AdH N Z V C Normal vanced EEPMOV EEPMOV.B — 4 if R4L ≠ 0 Repeat @R5→@R6 R5+1→R5 R6+1→R6 R4L–1→R4L Until R4L = 0 else next; — — — — — — 8+4n*2 8+4n*2 EEPMOV.W — 4 if R4 ≠ 0 Repeat @R5→@R6 R5+1→R5 R6+1→R6 R4L–1→R4L Until R4 = 0 else next; — — — — — — 8+4n*2 8+4n*2 Notes: 1.
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L AND.L #xx:32,ERd AND.L ERs,ERd — — BCC d:16 (BHS d:16) BCS d:8 (BLO d:8) — BLS d:8 — 4 — BHI d:16 — 5 — BHI d:8 BCC d:8 (BHS d:8) 4 — BRN d:16 (BF d:16) BLS d:16 5 — BRN d:8 (BF d:8) 4 5 4 5 4 5 — BRA d:16 (BT d:16) 4 7 — B BAND #xx:3,@aa:8 7 7 0 0 7 6 7 BRA d:8 (BT d:8) B BAND #xx:3,@ERd Bcc B ANDC #xx:8,CCR BAND #xx:3,Rd BAND B L AND.W #xx:16,Rd AND.W Rs,Rd B W W AND.B Rs,Rd 1 0 E B B AND.
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Rev. 3.
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BST BSR BSET BOR BNOT BLD BIXOR BIST BIOR Instruction 7 7 5 B B B B — BSET #xx:3,@aa:8 BSET Rn,Rd BSET Rn,@ERd BSET Rn,@aa:8 BSR d:8 BSR d:16 B B B BST #xx:3,@ERd BST #xx:3,@aa:8 7 7 5 6 — BST #xx:3,Rd 7 6 7 7 B BSET #xx:3,@ERd 7 7 B B BOR #xx:3,@aa:8 7 7 7 7 6 7 7 7 7 7 BSET #xx:3,Rd B B BOR #xx:3,@ERd B BNOT Rn,@aa:8 BOR #xx:3,Rd B B BNOT Rn,@ERd B BNOT Rn,Rd B BNOT #xx:3,@aa:8 B BLD #xx:3,@aa:8 BNOT #xx:3,@ERd B BLD #xx:3,@ERd B 7 B BLD #xx:3,Rd
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7 Rev. 3.00 Dec 13, 2004 page 208 of 258 REJ09B0213-0300 1 1 1 1 W W L L DEC.W #1,Rd DEC.W #2,Rd DEC.L #1,ERd DEC.L #2,ERd INC EXTU EXTS EEPMOV DIVXU DIVXS 1 B B W W INC.W #1,Rd INC.W #2,Rd L INC.B Rd W EXTU.L ERd L EXTU.W Rd W EXTS.L ERd — EXTS.W Rd — EEPMOV.B EEPMOV.W B W DIVXU.B Rs,Rd W DIVXS.W Rs,ERd DIVXU.W Rs,ERd B DIVXS.B Rs,Rd 0 0 0 1 1 1 1 7 7 5 5 0 0 1 DEC.B Rd B 0 1 DEC CMP.L ERs,ERd B CMP.L #xx:32,ERd 1 DAS Rd L L CMP.
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MOV LDC JSR JMP INC Instruction — — W W W W LDC @(d:24,ERs),CCR LDC @ERs+,CCR LDC @aa:16,CCR LDC @aa:24,CCR 0 0 0 0 0 B B B B B B B B B B B B B B B W W W MOV.B Rs,Rd MOV.B @ERs,Rd MOV.B @(d:16,ERs),Rd MOV.B @(d:24,ERs),Rd MOV.B @ERs+,Rd MOV.B @aa:8,Rd MOV.B @aa:16,Rd MOV.B @aa:24,Rd MOV.B Rs,@ERd MOV.B Rs,@(d:16,ERd) MOV.B Rs,@(d:24,ERd) MOV.B Rs,@–ERd MOV.B Rs,@aa:8 MOV.B Rs,@aa:16 MOV.B Rs,@aa:24 MOV.W #xx:16,Rd MOV.W Rs,Rd MOV.
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Rev. 3.00 Dec 13, 2004 page 210 of 258 REJ09B0213-0300 L L L L L L L L L L L L L L MOV.W Rs,@aa:24 MOV.L #xx:32,Rd MOV.L ERs,ERd MOV.L @ERs,ERd MOV.L @(d:16,ERs),ERd MOV.L @(d:24,ERs),ERd MOV.L @ERs+,ERd MOV.L @aa:16,ERd MOV.L @aa:24,ERd MOV.L ERs,@ERd MOV.L ERs,@(d:16,ERd) MOV.L ERs,@(d:24,ERd) MOV.L ERs,@–ERd MOV.L ERs,@aa:16 MOV.L ERs,@aa:24 NOP NEG MULXU NEG.L ERd — L NEG.W Rd NOP B W NEG.B Rd B W MULXU.B Rs,Rd MULXU.W Rs,ERd B W W MOV.W Rs,@aa:16 MULXS.W Rs,ERd W MOV.
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W L SHAL.W Rd SHAL.L ERd SHAR B SHAL.B Rd SHAL B W L SHAR.B Rd SHAR.W Rd SHAR.L ERd — RTS RTS L — ROTXR.L ERd RTE W ROTXR.W Rd L B ROTXL.L ERd ROTXR.B Rd W ROTXL.W Rd L B ROTR.L ERd ROTXL.B Rd B W ROTR.W Rd L ROTL.L ERd ROTR.B Rd W ROTL.W Rd L B PUSH.L ERn ROTL.B Rd W PUSH.W Rn RTE ROTXR ROTXL ROTR ROTL PUSH L POP.L ERn B W OR.L ERs,ERd ORC #xx:8,CCR L L OR.L #xx:32,ERd POP.W Rn 6 W OR.W Rs,Rd POP 7 W OR.
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Rev. 3.00 Dec 13, 2004 page 212 of 258 REJ09B0213-0300 W W L L SUB.W #xx:16,Rd SUB.W Rs,Rd SUB.L #xx:32,ERd SUB.L ERs,ERd XORC 6 W L L XOR.W Rs,Rd XOR.L #xx:32,ERd XOR.L ERs,ERd B 7 W XOR.W #xx:16,Rd XORC #xx:8,CCR 1 0 0 7 D B B XOR.B Rs,Rd 5 1 B 1 1 1 1 7 0 0 0 0 0 XOR.B #xx:8,Rd XOR B — SUBX Rs,Rd TRAPA #x:2 B SUBX #xx:8,Rd TRAPA SUBX SUBS L B SUB.
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Section 2 Instruction Descriptions Legend: IMM: abs: disp: rs, rd, rn: Immediate data (2, 3, 8, 16, or 32 bits) Absolute address (8, 16, or 24 bits) Displacement (8, 16, or 24 bits) Register field (4 bits specifying an 8-bit or 16-bit register. rs corresponds to operand symbols such as Rs, rd corresponds to operand symbols such as Rd, and rn corresponds to the operand symbol Rn.) ers, erd, ern: Register field (3 bits specifying a 32-bit register.
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AH Table 2.5 1 Rev. 3.00 Dec 13, 2004 page 214 of 258 REJ09B0213-0300 2 LDC 3 BL RTE BNE AND.B ANDC 6 BST TRAPA BEQ 8 OR XOR AND MOV D E F SUBX B C CMP MOV BVS SUB.W 9 Table 2.5 ADD Table 2.5 BVC SUB.B MOV.B Table 2.5 LDC 7 AND.W XOR.W BIST BLD BXOR BAND BILD BIOR BIXOR BIAND BSR BCS XOR.B XORG 5 A BOR OR.W RTS BCC OR.B ORG 4 Table 2.5 JMP BPL Table 2.5 Table 2.5 A MOV EEPMOV BMI Table 2.5 Table 2.5 B Instruction when most significant bit of BH is 1.
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DEC SUBS DAS BRA MOV MOV 1B 1F 58 79 7A ADD ADD BRN NOT 17 1A ROTXL ROTXR 13 SHLR 12 SHLL 0F 11 DAA 0B 1 AL 1st byte AH 10 INC ADDS 0A MOV 0 AH AL 01 BH Operation Code: CMP CMP BHI 2 BH SUB SUB BLS NOT ROTXR ROTXL SHLR SHLL 3 BL 2nd byte Table 2.
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BCLR MULXS 2 3 Rev. 3.00 Dec 13, 2004 page 216 of 258 REJ09B0213-0300 BSET BSET BNOT BNOT BCLR BCLR Notes: 1. r is a register field. 2. aa is an absolute address field. 7Faa7 *2 7Faa6*2 BTST BCLR BTST BNOT 7Eaa7*2 BSET 7Eaa6*2 7Dr07 *1 7Dr06 *1 BOR BOR BIOR BIOR OR 4 CL 3rd byte CH DIVXS BL BTST BNOT DIVXS 1 BH 7Cr07 *1 BSET MULXS 0 AL 2nd byte BTST CL AH 1st byte 7Cr06 *1 01F06 01D05 01C05 AHALBHBLCH Operation Code: Table 2.
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Section 2 Instruction Descriptions 2.6 Number of States Required for Instruction Execution The tables in this section can be used to calculate the number of states required for instruction execution by the H8/300H CPU. Table 2.8 indicates the number of instruction fetch, data read/write, and other cycles occurring in each instruction. Table 2.7 indicates the number of states required for each size.
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Section 2 Instruction Descriptions Table 2.
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Section 2 Instruction Descriptions Table 2.8 Number of Cycles in Instruction Execution Instruction Fetch Branch Address Read Stack Operation Byte Data Access Word Data Access Internal Operation J K L M N Instruction Mnemonic I ADD ADD.B #xx:8,Rd 1 ADD.B Rs,Rd 1 ADD.W #xx:16,Rd 2 ADD.W Rs,Rd 1 ADD.L #xx:32,ERd 3 ADD.L ERs,ERd 1 ADDS ADDS #1/2/4,ERd 1 ADDX ADDX #xx:8,Rd 1 ADDX Rs,Rd 1 AND AND.B #xx:8,Rd 1 AND.B Rs,Rd 1 AND.W #xx:16,Rd 2 AND.W Rs,Rd 1 AND.
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Section 2 Instruction Descriptions Instruction Fetch Branch Address Read Stack Operation Byte Data Access Word Data Access Internal Operation J K L M N Instruction Mnemonic I Bcc BGT d:8 2 BLE d:8 2 BCLR BIAND BILD BIOR BRA d:16 (BT d:16) 2 2 BRN d:16 (BF d:16) 2 2 BHI d:16 2 2 BLS d:16 2 2 BCC d:16 (BHS d:16) 2 2 BCS d:16 (BLO d:16) 2 2 BNE d:16 2 2 BEQ d:16 2 2 BVC d:16 2 2 BVS d:16 2 2 BPL d:16 2 2 BMI d:16 2 2 BGE d:16 2 2 BLT d:16 2 2 BG
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Section 2 Instruction Descriptions Instruction Fetch Branch Address Read Stack Operation Byte Data Access Word Data Access Internal Operation J K L M N Instruction Mnemonic I BIST BIST #xx:3,Rd 1 BIST #xx:3,@ERd 2 2 BIST #xx:3,@aa:8 2 2 BIXOR #xx:3,Rd 1 BIXOR #xx:3,@ERd 2 1 1 BIXOR BLD BNOT BOR BSET BSR BIXOR #xx:3,@aa:8 2 BLD #xx:3,Rd 1 BLD #xx:3,@ERd 2 1 BLD #xx:3,@aa:8 2 1 BNOT #xx:3,Rd 1 BNOT #xx:3,@ERd 2 2 BNOT #xx:3,@aa:8 2 2 BNOT Rn,Rd 1 BNOT Rn,
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Section 2 Instruction Descriptions Instruction Fetch Branch Address Read Stack Operation Byte Data Access Word Data Access Internal Operation J K L M N Instruction Mnemonic I BTST BTST #xx:3,Rd 1 BTST #xx:3,@ERd 2 1 BTST #xx:3,@aa:8 2 1 BTST Rn,Rd 1 BTST Rn,@ERd 2 1 BTST Rn,@aa:8 2 1 BXOR #xx:3,Rd 1 BXOR CMP BXOR #xx:3,@ERd 2 1 BXOR #xx:3,@aa:8 2 1 CMP.B #xx:8,Rd 1 CMP.B Rs,Rd 1 CMP.W #xx:16,Rd 2 CMP.W Rs,Rd 1 CMP.L #xx:32,ERd 3 CMP.
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Section 2 Instruction Descriptions Instruction Fetch Branch Address Read Stack Operation Byte Data Access Word Data Access Internal Operation J K L M N Instruction Mnemonic I JMP JMP @ERn 2 JMP @aa:24 JMP @@aa:8 JSR JSR @ERn JSR @aa:24 JSR @@aa:8 LDC MOV 2 2 Advanced 2 2 2 Normal 2 1 Advanced 2 2 Normal 2 1 Advanced 2 2 2 Normal 2 1 2 2 Advanced 2 2 2 Normal 2 1 1 LDC #xx:8,CCR 1 LDC Rs,CCR 1 LDC @ERs,CCR 2 1 LDC @(d:16,ERs),CCR 3 1 LDC @(d:
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Section 2 Instruction Descriptions Instruction Fetch Branch Address Read Stack Operation Byte Data Access Word Data Access Internal Operation J K L M N Instruction Mnemonic I MOV MOV.W #xx:16,Rd 2 MOV.W Rs,Rd 1 MOV.W @ERs,Rd 1 1 MOV.W @(d:16,ERs),Rd 2 1 MOV.W @(d:24,ERs),Rd 4 1 MOV.W @ERs+,Rd 1 1 MOV.W @aa:16,Rd 2 1 MOV.W @aa:24,Rd 3 1 MOV.W Rs,@ERd 1 1 MOV.W Rs,@(d:16,ERd) 2 1 MOV.W Rs,@(d:24,ERd) 4 1 MOV.W Rs,@–ERd 1 1 MOV.W Rs,@aa:16 2 1 MOV.
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Section 2 Instruction Descriptions Instruction Fetch Branch Address Read Stack Operation Byte Data Access Word Data Access Internal Operation J K L M N Instruction Mnemonic I NEG NEG.B Rd 1 NEG.W Rd 1 NEG.L ERd 1 NOP NOP 1 NOT NOT.B Rd 1 OR NOT.W Rd 1 NOT.L ERd 1 OR.B #xx:8,Rd 1 OR.B Rs,Rd 1 OR.W #xx:16,Rd 2 OR.W Rs,Rd 1 OR.L #xx:32,ERd 3 OR.L ERs,ERd 2 ORC ORC #xx:8,CCR 1 POP POP.W Rn 1 1 2 POP.L ERn 2 2 2 PUSH.W Rn 1 1 2 PUSH.
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Section 2 Instruction Descriptions Instruction Fetch Branch Address Read Stack Operation Byte Data Access Word Data Access Internal Operation J K L M N Instruction Mnemonic I SHAL SHAL.B Rd 1 SHAL.W Rd 1 SHAR SHLL SHLR SHAL.L ERd 1 SHAR.B Rd 1 SHAR.W Rd 1 SHAR.L ERd 1 SHLL.B Rd 1 SHLL.W Rd 1 SHLL.L ERd 1 SHLR.B Rd 1 SHLR.W Rd 1 SHLR.
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Section 2 Instruction Descriptions Instruction Fetch Branch Address Read Stack Operation Byte Data Access Word Data Access Internal Operation J K L M N Instruction Mnemonic I XOR XOR.B #xx:8,Rd 1 XOR.B Rs,Rd 1 XOR.W #xx:16,Rd 2 XORC XOR.W Rs,Rd 1 XOR.L #xx:32,ERd 3 XOR.L ERs,ERd 2 XORC #xx:8,CCR 1 Notes: 1. When n bytes of data are transferred. Rev. 3.
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Section 2 Instruction Descriptions 2.7 Condition Code Modification This section indicates the effect of each CPU instruction on the condition code. The notation used in the table is defined below.
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Section 2 Instruction Descriptions N Z V C ↔ ↔ ↔ ADD H ↔ Instruction Condition Code Modification ↔ Table 2.9 Definition H=Sm–4·Dm–4+Dm–4·/Rm–4+Sm–4·/Rm–4 N=Rm Z = / R m · / R m – 1 · ... · / R 0 V=Sm·Dm·/Rm+/Sm·/Dm·Rm ↔ ↔ ADDX ↔ — — — ↔ — — ↔ C=Sm·Dm+Dm·/Rm+Sm·/Rm ADDS H=Sm–4·Dm–4+Dm–4·/Rm–4+Sm–4·/Rm–4 N=Rm Z = Z ' · / R m · ... · / R 0 V=Sm·Dm·/Rm+/Sm·/Dm·Rm ↔ — ↔ C=Sm·Dm+Dm·/Rm+Sm·/Rm AND O — N=Rm — — ↔ ↔ — — ↔ BAND ↔ ↔ ↔ Z = / R m · / R m – 1 · ...
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H N Z V C ↔ ↔ ↔ ↔ Instruction CMP ↔ Section 2 Instruction Descriptions Definition H=Sm–4·/Dm–4+/Dm–4·Rm–4+Sm–4·Rm–4 N=Rm Z = / R m · / R m – 1 · ... · / R 0 V=/Sm·Dm·/Rm+Sm·/Dm·Rm * ↔ * ↔ DAA ↔ C=Sm·/Dm+/Dm·Rm+Sm·Rm N=Rm Z = / R m · / R m – 1 · ... · / R 0 * ↔ * ↔ DAS ↔ C: decimal arithmetic carry N=Rm Z = / R m · / R m – 1 · ... · / R 0 ↔ ↔ — ↔ C: decimal arithmetic borrow DEC — N=Rm Z = / R m· / R m – 1 · ...
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H N Z — ↔ Instruction MULXS ↔ Section 2 Instruction Descriptions V C Definition — — N=R2m ↔ ↔ — — — ↔ — — NEG ↔ MULXU ↔ Z = R 2 m · R 2 m – 1 · ... · / R 0 H=Dm–4+Rm–4 N=Rm Z = / R m · / R m – 1 · ... · R 0 V=Dm·Rm — ↔ OR — — — — ↔ — — NOT O — N=Rm ↔ NOP ↔ C=Dm+Rm O — N=Rm Z = / R m · / R m – 1 · ... · / R 0 O ↔ ↔ — ↔ ↔ POP ↔ ↔ ↔ Z = / R m · / R m – 1 · .... · / R 0 ORC Stores the corresponding bits of the result — N=Rm — ↔ PUSH ↔ Z = / R m · / R m – 1 · .
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H N Z V C — ↔ ↔ ↔ Instruction SHAL ↔ Section 2 Instruction Descriptions Definition N=Rm Z = / R m · / R m – 1 · ... · / R 0 V=Dm·/Dm–1+/Dm·Dm–1 O ↔ — ↔ SHAR ↔ C=Dm N=Rm Z = / R m · / R m – 1 · ... · / R 0 O ↔ ↔ — ↔ C=D0 SHLL N=Rm Z = / R m · / R m – 1 · ... · / R 0 O ↔ — ↔ SHLR ↔ C=Dm N=Rm Z = / R m · / R m – 1 · ... · / R 0 — — — — — SUB ↔ ↔ STC ↔ — — — ↔ — — ↔ C=D0 SLEEP H=Sm–4·/Dm–4+/Dm–4·Rm–4+Sm–4·Rm–4 N=Rm Z = / R m · / R m – 1 · ...
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Section 2 Instruction Descriptions 2.8 Bus Cycles During Instruction Execution Table 2.10 indicates the bus cycles during instruction execution by the H8/300H CPU. For the number of states per bus cycle, see table 2.7, Number of States per Cycle.
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Section 2 Instruction Descriptions Figure 2.1 shows timing waveforms for the address bus and the RD and WR (HWR or LWR) signals during execution of the above instruction with an 8-bit bus, using 3-state access with no wait states. φ Address bus RD WR (HWR or LWR) High level R:W 2nd Fetching 3rd byte of instruction Fetching 4th byte of instruction Internal operation R:W EA Fetching 1st byte of jump address Fetching 2nd byte of jump address HWR or LWR) Figure 2.
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1 R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT BRN d:8 (BF d;8) BHI d:8 BLS d:8 BCC d:8 (BHS d;8) BCS d:8 (BLO d;8) BNE d:8 BEQ d:8 BVC d:8 BVS d:8 BPL d:8 BMI d:8 R:W EA R:W EA R:B EA BRA d:8 (BT d;8) R:B EA R:W 2nd ANDC #xx:8,CCR R:W NEXT R:W 3rd BAND #xx:3,@aa:8 R:W NEXT AND.L ERs,ERd R:W NEXT R:W 2nd AND.L #xx:32,ERd R:W NEXT R:W 2nd R:W 2nd AND.
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R:W EA R:W EA R:W NEXT R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd BGT d:8 BLE d:8 BRA d:16 (BT d;16) BRN d:16 (BF d;16) BHI d:16 BLS d:16 BCC d:16 (BHS d;16) BCS d:16 (BLO d;16) BNE d:16 BEQ d:16 Rev. 3.
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R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd BCLR #xx:3,@ERd BCLR #xx:3,@aa:8 BCLR Rn,Rd BCLR Rn,@ERd BCLR Rn,@aa:8 BIAND #xx:3,Rd BIAND #xx:3,@ERd BIAND #xx:3,@aa:8 BILD #xx:3,Rd BILD #xx:3,@ERd BILD #xx:3,@aa:8 BIOR #xx:8,Rd BIOR #xx:8,@ERd BIOR #xx:8,@aa:8 BIST
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Rev. 3.00 Dec 13, 2004 page 238 of 258 REJ09B0213-0300 R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd BTST #xx:3,@aa:8 BTST Rn,Rd BTST Rn,@ERd BTST Rn,@aa:8 BXOR #xx:3,Rd BXOR #xx:3,@ERd BXOR #xx:3,@aa:8 R:W 2nd R:W 2nd EEPMOV.B EEPMOV.W R:W NEXT R:W NEXT DIVXU.W Rs,ERd R:W NEXT DEC.L #1/2,ERd DIVXU.B Rs,Rd R:W NEXT DEC.W #1/2,Rd R:W 2nd R:W NEXT DEC.B Rd R:W 2nd R:W NEXT DAS Rd DIVXS.W Rs,ERd R:W NEXT DAA Rd DIVXS.B Rs,Rd R:W 2nd R:W NEXT CMP.L ERs,ERd CMP.W Rs,Rd CMP.
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1 R:W NEXT MOV.B #xx:8,Rd R:W 2nd R:W 2nd LDC @aa:24,CCR MOV.B @(d:24,ERs),Rd R:W 2nd LDC @aa:16,CCR R:W 2nd R:W 2nd LDC @ERs+,CCR MOV.B @(d:16,ERs),Rd R:W 2nd LDC @(d:24,ERs),CCR R:W NEXT R:W 2nd LDC @(d:16,ERs),CCR R:W NEXT R:W 2nd LDC @ERs,CCR MOV.B @ERs,Rd R:W NEXT LDC Rs,CCR MOV.
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R:W NEXT R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd MOV.W Rs,Rd MOV.W @ERs,Rd MOV.W @(d:16,ERs),Rd MOV.W @(d:24,ERs),Rd MOV.W @ERs+,Rd MOV.W @aa:16,Rd MOV.W @aa:24,Rd MOV.W Rs,@ERd MOV.W Rs,@(d:16,ERd) MOV.W Rs,@(d:24,ERd) MOV.W Rs,@–ERd MOV.W Rs,@aa:16 MOV.W Rs,@aa:24 MOV.L #xx:32,ERd MOV.L ERs,ERd MOV.L @ERs,ERd MOV.L @(d:16,ERs),ERd MOV.L @(d:24,ERs),ERd MOV.L @ERs+,ERd R:W 2nd MOV.
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R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd MOV.L ERs,@(d:24,ERd) MOV.L ERs,@–ERd MOV.L ERs,@aa:16 MOV.L ERs,@aa:24 MOVFPE @aa:16,Rd MOVTPE Rs,@aa:16 R:W NEXT R:W NEXT R:W 2nd ORC #xx:8,CCR POP.W Rn POP.L ERn R:W 2nd R:W 2nd OR.L ERs,ERd OR.W Rs,Rd OR.L #xx:32,ERd R:W 2nd R:W NEXT OR.W #xx:16,Rd R:W NEXT R:W NEXT NOT.L ERd R:W NEXT R:W NEXT NOT.W Rd OR.B Rs,Rd R:W NEXT NOT.B Rd OR.B #xx:8,Rd R:W NEXT NEG.W Rd R:W NEXT R:W NEXT NEG.B Rd NOP R:W NEXT MULXU.W Rs,ERd NEG.
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Rev. 3.00 Dec 13, 2004 page 242 of 258 REJ09B0213-0300 R:W NEXT R:W NEXT R:W NEXT STC CCR,Rd SHLR.W Rd SLEEP R:W NEXT SHLR.B Rd SHLR.L ERd R:W NEXT R:W NEXT SHLL.L ERd R:W NEXT SHAR.L ERd R:W NEXT R:W NEXT SHAR.W Rd SHLL.W Rd R:W NEXT SHAR.B Rd SHLL.B Rd R:W NEXT R:W NEXT SHAL.L ERd R:W NEXT R:W NEXT R:W NEXT Advanced SHAL.W Rd R:W NEXT Normal RTS SHAL.B Rd R:W NEXT R:W NEXT ROTXR.W Rd RTE R:W NEXT ROTXR.B Rd ROTXR.L ERd R:W NEXT R:W NEXT ROTXL.
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R:W 2nd R:W NEXT STC CCR,@aa:24 SUB.B Rs,Rd R:W (*6) Advanced R:W VEC Advanced R:W (*6) R:W VEC Reset exception handling Normal R:W NEXT Normal XORC #xx:8,CCR Interrupt exception handling R:W 2nd R:W 2nd XOR.W Rs,Rd XOR.L ERs,ERd R:W NEXT XOR.W #xx:16,Rd XOR.L #xx:32,ERd R:W NEXT R:W 2nd XOR.B Rs,Rd R:W NEXT R:W NEXT Advanced XOR.B #xx8,Rd R:W NEXT R:W NEXT SUBX #xx:8,Rd Normal R:W NEXT SUBS #1/2/4,ERd TRAPA #x:2 R:W NEXT SUB.L ERs,ERd SUBX Rs,Rd R:W 2nd R:W NEXT SUB.
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Section 2 Instruction Descriptions Notes: 1. EAs is the contents of ER5. EAd is the contents of R6. 2. EAs is the contents of ER5. EAd is the contents of R6. Both registers are incremented by 1 after execution of the instruction. n is the initial value of R4L or R4. If n = 0, these bus cycles are not executed. 3. The number of states required for byte read or write varies from 9 to 16. 4. Starting address after return. 5. Starting address of the program. 6.
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Section 3 Processing States Section 3 Processing States 3.1 Overview The CPU has five main processing states: the program execution state, exception handling state, power-down state, reset state, and bus-released state. The power-down state includes sleep mode, software standby mode, and hardware standby mode. Figure 3.1 shows a diagram of the processing states. Figure 3.2 indicates the state transitions. For details, refer to the relevant microcontroller hardware manual.
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Section 3 Processing States End of bus-released state Bus request do r En Bus request Bus request completion est equ r t rup EE Bus-released state Inte P ith =1 EE w BY SL ion 0 t SS c = ith tru Y nw ins SB S ctio stru P in SL re End lea o fe se f b xc u ep Bu d st sRe t at i s o qu e n r eq es t fo hand ue st re lin g xc ep tio nh an dli ng Program execution state External interrupt Software standby mode RES high Exception-handling state Sleep mode Reset state*1 STBY high, RES low Har
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Section 3 Processing States 3.3.1 Types of Exception Handling and Their Priority Exception handling is performed for resets, interrupts, and trap instructions. Table 3.1 indicates the types of exception handling and their priority. Table 3.
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Section 3 Processing States 3.3.2 Exception-Handling Sequences Reset Exception Handling: Reset exception handling has the highest priority. The reset state is entered when the RES signal goes low. Then, if RES goes high again, reset exception handling starts when the reset condition is satisfied. Refer to the relevant microcontroller hardware manual for details about the reset condition.
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Section 3 Processing States SP – 4 SP – 3 SP – 2 SP – 1 SP (ER7) Stack area SP (ER7) SP + 1 SP + 2 SP + 3 SP + 4 Before exception handling starts Pushed on stack CCR CCR* PCH PCL Even address After exception handling ends (a) Stack structure in normal mode SP – 4 SP – 3 SP – 2 SP – 1 SP (ER7) Stack area SP (ER7) SP + 1 SP + 2 SP + 3 SP + 4 Before exception handling starts Pushed on stack CCR PCE PCH PCL Even address After exception handling ends (b) Stack structure in advanced mode Legend: P
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Section 3 Processing States 3.4 Bus-Released State This is a state in which the bus has been released in response to a bus request from a bus master other than the CPU. While the bus is released, the CPU halts except for internal operations. For further details, refer to the relevant microcontroller hardware manual. For further details, refer to the relevant microcontroller hardware manual. 3.5 Reset State When the RES input goes low all current processing stops and the CPU enters the reset state.
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Section 3 Processing States 3.6.3 Hardware Standby Mode A transition to hardware standby mode is made when the STBY input goes low. As in software standby mode, the CPU and clock halt and the on-chip supporting modules are reset, but as long as a specified voltage is supplied, on-chip RAM contents are retained. Rev. 3.
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Section 3 Processing States Rev. 3.
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Section 4 Basic Timing Section 4 Basic Timing 4.1 Overview The CPU is driven by a clock, denoted by the symbol φ. One cycle of the clock is referred to as a “state.” The memory cycle or bus cycle consists of two or three states. Different methods are used to access on-chip memory, on-chip supporting modules, and external devices. Refer to the relevant microcontroller hardware manual for details. 4.2 On-Chip Memory (RAM, ROM) For high-speed processing, on-chip memory is accessed in two states.
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Section 4 Basic Timing Bus cycle T1 state T2 state φ Address bus Address AS High RD High WR (HWR or LWR) High Data bus high-impedance state Figure 4.2 Pin States during On-Chip Memory Access Rev. 3.
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Section 4 Basic Timing 4.3 On-Chip Supporting Modules The on-chip supporting modules are accessed in three states. The data bus is 8 bits or 16 bits wide. Figure 4.3 shows the access timing for the on-chip supporting modules. Figure 4.4 shows the pin states. Bus cycle T1 state T2 state T3 state φ Internal address bus Address Internal read signal Internal data bus (read access) Read data Internal write signal Internal data bus (write access) Write data Figure 4.
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Section 4 Basic Timing Bus cycle T1 state T2 state T3 state φ Address Address bus AS High RD High WR (HWR or LWR) High Data bus high-impedance state Figure 4.4 Pin States during On-Chip Supporting Module Access 4.4 External Data Bus The external data bus is accessed with 8-bit or 16-bit bus width in two or three states. Figure 4.5 shows the read timing for two-state or three-state access. Figure 4.6 shows the write timing for two-state or three-state access.
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Section 4 Basic Timing Read cycle T1 state T2 state φ Address bus Address AS RD Data bus Read data (two-state access) Read cycle T1 state T2 state T3 state φ Address bus Address AS RD Data bus Read data (three-state access) Figure 4.5 External Device Access Timing (1) Read Timing Rev. 3.
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Section 4 Basic Timing Write cycle T1 state T2 state φ Address bus Address AS WR (HWR or LWR) Data bus Write data (a) Two-state access Write cycle T1 state T2 state T3 state φ Address bus Address AS WR (HWR or LWR) Data bus Write data (b) Three-state access Figure 4.6 External Device Access Timing (2) Write Timing Rev. 3.
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Renesas 16-Bit Single-Chip Microcomputer Software Manual H8/300H Series Publication Date: 1st Edition, August 1993 Rev.3.00, December 13, 2004 Published by: Sales Strategic Planning Div. Renesas Technology Corp. Edited by: Technical Documentation & Information Department Renesas Kodaira Semiconductor Co., Ltd. © 2004. Renesas Technology Corp. All rights reserved. Printed in Japan.
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Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan RENESAS SALES OFFICES http://www.renesas.com Refer to "http://www.renesas.com/en/network" for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501 Renesas Technology Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K.
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H8/300H Series Software Manual 1753, Shimonumabe, Nakahara-ku, Kawasaki-shi, Kanagawa 211-8668 Japan REJ09B0213-0300