Technical information

Section 2 Instruction Descriptions
Rev. 3.00 Dec 13, 2004 page 186 of 258
REJ09B0213-0300
2.2.62 TRAPA
TRAPA (TRAP Always) Trap Unconditionally
Operation
PC → @–SP
CCR → @–SP
<Vector> → PC
Assembly-Language Format
TRAPA #x:2
Operand Size
—
Condition Code
IUIHUNZVC
1 ∆ —
*1
—— ———
I: Always set to 1.
U: See notes.
H: Previous value remains unchanged.
N: Previous value remains unchanged.
Z: Previous value remains unchanged.
V: Previous value remains unchanged.
C: Previous value remains unchanged.
Description
This instruction pushes the program counter (PC) and condition-code register (CCR) on the stack,
then sets the I bit to 1 and branches to a new address. The new address is the contents of the vector
address corresponding to the specified vector number. The PC value pushed on the stack is the
starting address of the next instruction after the TRAPA instruction.
Vector Address
#x
Normal Mode Advanced Mode
0 H'0010 to H'0011 H'000020 to H'000023
1 H'0012 to H'0013 H'000024 to H'000027
2 H'0014 to H'0015 H'000028 to H'00002B
3 H'0016 to H'0017 H'00002C to H'00002F
Operand Format and Number of States Required for Execution
Instruction Format
Addressing
Mode
Mnemonic Operands
1st byte 2nd byte 3rd byte 4th byte
No. of
States
Register direct TRAPA #x:2 5 7 00 IMM 0 14
Notes
1. CCR bit 6 is set to 1 when used as an interrupt mask bit, but retains its previous value when
used as a user bit.
2. The stack and vector structure differ between normal mode and advanced mode.