Specifications

10
Trap instruction
exceptions (TRAPA)
These exceptions start when a TRAPA
instruction is executed in program
execution state. The TRAPA instruction
has four vectors as specified by its
argument. This exception can be used as
an efficient mechanism for calling
operating system functions,as it takes
only 2 Byte to execute a TRAPA
instruction, compared to 4 Byte for a
BSR and 8 Byte for a JSR.
Interrupt
Controller
on H8/300H
The H8/300H interrupt controller can
be operated in two modes,either
maintaining compatibility with the
standard H8/300 interrupt controller, or
in a more advanced mode.
• H8/300 compatible
mode
In this mode the acceptance of
maskable interrupts is controlled by the
I-bit in the CCR. If I is set,then all
interrupts are disabled (except NMI)
and if I is cleared then all interrupts are
enabled. When an interrupt is
accepted,the controller automatically
sets the I-bit,thus disabling any other
maskable interrupts for the duration of
the interrupt service routine (ISR),
unless it is cleared by the users code.
• H8/300H advanced
mode
To increase the power of the interrupt
controller, an extra interrupt status bit
is included in the condition code
register, known as the UI or User
Interrupt bit. This extended operation
allows the user to specify raised
priority interrupt sources,which are
capable of interrupting a low priority
ISR which is already running. The
priority of individual interrupt sources
is programmed in a number of
interrupt priority registers (IPR).
Interrupt
controller
on H8S
The interrupt controllers within the H8S
family differ,depending on the particular
H8S series. H8S/2655 has an interrupt
controller that provides four modes
(0...3) and the other series provide a
subset.
• Mode 0
This mode provides the mechanism
known from H8/300. Acceptance is
solely controlled by the I-bit.
• Mode 1
In this mode acceptance is controlled
by I and UI,thus providing functional
compatibility with H8/300H.
• Mode 2
This mode provides an 8-level
priority mechanism controlled by bits
I0.. I2 in the EXR register. Priorities
for each interrupt source can be
programmed in a set of IPR registers.
• Mode 3
This mode combines mode 1 and 2,
effectively providing up to 9 levels of
priority.
H8S/265x derivatives can use modes
0.. 4, H8S/263x, H8S/23xx,H8S/223x
and 222x can use modes 0 and 2,and
H8S/224x and 21xx can use modes 0
and 1.
Exceptions
and
Interrupt
Controller
H8/300H and H8S feature a
sophisticated interrupt system, that allows
to respond quickly to asynchronous
events. The worst case interrupt response
time is 2.6µs for H8/300H (at 16MHz)
and 1.5µs for H8S (at 20MHz).
Because almost every interrupt source
has its own vector,the interrupt service
routine can immediately start to do some
useful work,instead of polling status flags
to find the cause of the interrupt.
If two or more exceptions occur
simultaneously, they are accepted and
processed in order of priority. Software
interrupts (‘Trap’) are accepted at all
times,in the program execution state.
Interrupts are handled as follows:
• The PC and the CCR are pushed
onto the stack
• The interrupt mask bits are updated
• A vector address corresponding to the
exception source is generated,and
program execution starts from that
address
External interrupts
(NMI and IRQ)
H8/300H and H8S have several external
interrupts, including one non-maskable-
interrupt (NMI). NMI can be
programmed to be activated on either
the rising or the falling edge. Interrupt
request pins (IRQ) can be programmed
to recognise either a low level or a low
going edge on H8/300H,and on H8S
can be programmed to recognise a low
level, a rising or a falling edge or both
edges.