Specifications

14
Direct Memory Access
Controller (DMAC)
In a system with a high performance
CPU and with large memory, a Direct
Memory Access Controller will
significantly increase system performance.
Instead of wasting CPU performance to
move data between peripherals and
memory, virtually all of the CPU
performance can be used for calculations,
while the DMA handles the data
transfers.
If combined with other peripherals,such
as timers, SCI’s or the real time outputs
of the TPC/PPG,entire autonomous
subsystems can be built,for example to
drive stepper motors or to communicate
with LCD modules or keyboards with
hardly any CPU intervention.
As H8S almost triples the CPU
performance of H8/300H,the DMAC on
H8S has improvements over the H8/300H
DMAC,in order to keep CPU and
DMAC performance in a good balance.
But let us first have a look at the common
features:
• 4 channels in short address mode
(used for transfers between internal
IO and memory)*
• 2 channels in full address mode (used
for transfers between memory and
memory, or between external IO and
memory)
• Byte or word transfer selectable
• address increment,decrement or fixed
selectable,depending on mode
• DMA transfer request possible by
timer,SCI0 and external request,
depending on mode
• Interrupt request possible after each
transfer or after specified number of
transfers
Some of the major improvements on
H8S are:
• A special transfer mode has been
added,single address mode,where
both resources must be external and
data is transferred in fly-by fashion for
fastest transfer speed.
• More transfer request sources,e.g.
A/D conversion end interrupt and at
least 2 SCI can request a transfer
Short Address Mode
In this mode either the source or
destination address is limited to only 8
bits (H8/300H) or 16 bits (H8S),with
the upper bits being automatically set to
logic ‘1’. This allows to access the
internal IO registers. The other address
is 24 bits wide, so that the entire
memory space is accessible.
Within short address mode there is ‘IO
mode’(called sequential mode on H8S),
where the full address can be
automatically incremented or
decremented,‘idle mode’ with the full
address being fixed and ‘repeat mode’,
which allows cyclic data buffers to be
automatically transferred. Cyclic data
buffers are useful for many applications,
e. g. to output a control pattern for a
stepper motor.
Full Address
Mode
To perform memory to
memory transfers the full
address mode can be
used. Here,the source
and destination addresses
are 24-bits wide each,
and therefore memory to
memory transfer can be
* 8 channels on H8/3003
External
memory
External
device
(Read)
(Write)
RD
HWR, LWR
A
23
to A
0
H8S/2655
D
15
to D
0
(high impedance)
DACK
Address bus
Data bus
performed between any area of the full
16MBytes address space. This mode
allows either a single transfer to occur
per request (‘normal mode’), or for a
block of data to be moved (‘block
transfer mode’). In ‘normal mode’ and
with ‘auto-request’ enabled, the DMAC
can be set up in a burst mode,taking
over the bus from the processor until all
the transfers are complete, or in a cycle
steal mode where the processor and the
DMAC share the bus.
Single address
mode (H8S)
Figure 13 illustrates the new single
address mode. In single address mode a
transfer of data is carried out directly
between the data busses of two external
devices,e.g. an external peripheral and
DRAM. The advantage is the speed of
the transfer,because the data is moved in
a single cycle without a temporary
storage. Either the source or the
destination must be a device which can
be accessed with a strobe alone,using the
DACK pin. The address bus is used to
access the other resource.
Figure 13