Specifications

15
Data Transfer Controller (DTC)
Analysis of many applications that use a
DMAC has shown that a substantial part
of these applications do not require the
maximum speed of data transfers. These
applications use a DMAC mainly to
reduce CPU overhead,allowing the
CPU to use its performance for
calculations.
Therefore Hitachi conceived another
peripheral to autonomously handle data
transfers,the Data Transfer Controller
(DTC). The DTC puts emphasise on
offloading the CPU from data transfer
tasks,while providing a maximum of
flexibility. Unlike a DMAC the DTC can
handle a very large number of transfer
channels and transfers can be requested by
almost any peripheral that can request an
interrupt as well as by software. On the
other hand a DTC transfer is
approximately 5 times slower than a DMA
transfer (1000ns as opposed to 200ns at
20MHz,assuming e.g. source is a
peripheral and destination memory). In
block transfer mode the DTC overhead is
divided by the number of transfers within
Address
ø
DTC activation
request
DTC
request
Data transfer Data transfer
Transfer
information
write
Transfer
information
write
Transfer
information
read
Transfer
information
read
Vector read
Read Write Read Write
the block,thus practically eliminating the
overhead penalty.
Also, a single trigger can request multiple
transfers (chain mode).
This feature could,for example,be used
to move the result of an analogue-to-
digital conversion to a circular buffer in
RAM,followed by automatic
reprogramming of the ADC to perform
other conversions. If the tasks given to
the ADC are stored in a table in ROM,
which is then used by the DTC in a
round-robbing scheme, while the
conversion results are stored in a
corresponding number of circular buffers
in RAM,the DTC and the ADC could
perform a large set of completely
different tasks without any CPU
intervention whatsoever.
Figure 14 shows the timing of such a
chain transfer. Please note that one cycle
of phi is only 50ns at 20MHz. As can be
seen,the DTC vector is read after a
transfer request in only one cycle, each
move of the transfer information
between DTC RAM and DTC registers
takes 3 cycles and the actual data transfers
take 2 cycles (minimum).
The DTC could be seen as a DMAC
with only a single channel implemented
in hardware. The registers for the
destination and source address,for the
transfer mode and the transfer count
actually exist only once. However,these
registers are loaded with the information
to be used for a particular transfer from
RAM. That means that the structure of
the DTC registers is mirrored in a special
DTC RAM as many times as the
designer has chosen to implement
transfer channels. Each transfer can be
specified to be byte- or word-wide,
source and destination addresses can both
be 24-bits wide (i.e. cover the full
address range). Source and destination
addresses can be either incremented or
decremented (by 1 or 2),or can be fixed.
A CPU interrupt can be requested for
the interrupt that triggered the DTC
transfer,either after each transfer or after
the specified number of transfers have
been performed.
Figure 14