Specifications

19
“mishap’in the system (such as a noise
induced software crash) is rectified as
quickly as possible.
The principle behind a watchdog timer
is very simple - a counter is constantly
counting upwards,and correctly
operating software ensures that this
counter never overflows by continuously
resetting the count. If the software
crashes and the counter overflows,the
watchdog “barks” and sends some
stimulus to the microcontroller (normally
a reset) to restart system operations in a
controlled manner.
All H8/300H devices are equipped with
a timer,which can be used either as a
watchdog or as an interval timer. Its
‘bark’is a reset if it is used as a watchdog.
If used as interval timer,each overflow
generates an interrupt.
Watchdog Timer
(WDT) on H8S
The WDT on H8S has some
improvements over the WDT on
H8/300H.
It has an WDTOVF-pin that can signal
the watchdog overflow to the outside
world. It can select much slower clock
sources up to phi/131072,which allows
up to 1.68s (at 20MHz) for the software
to reset the watchdog before overflow.
Watchdog Timer
(WDT)
operating on 32KHz
subclock
On some H8S derivatives a second WDT
is implemented,which is operating off a
32KHz subclock. This subclock can be
divided by 2 to 256 before it is used as
counter input clock. Hence,the final
overflow rate can be as low as 32KHz
divided by 256x256 = once every two
seconds. This WDT can request an
interrupt, reset or NMI. If an interrupt
is requested this WDT is useful to update
a software real time clock. For this
usage, every peripheral module on the
device is turned off and the CPU is
brought into sleep mode. Then the
WDT wakes up the CPU every second,
for example, the CPU updates the the
software real time clock registers (usually
kept in RAM) and goes to sleep again, if
no other activity is pending.