Specifications

21
Serial Communications Interface (SCI)
20MHz for H8/300H and over 4Mbit/s
at 25MHz for H8S.
The H8S and the H8/300H serial ports
also support multiprocessor
communications using a master slave
configuration in addition to the standard
modes.
In this mode, communication between
devices is performed using an additional
multiprocessor bit (MPB) which is added
to the data transmitted. This bit is used
to differentiate between data frames and
address frames. Thus,any frame sent
from the master with the MPB set to
one can be used to activate the required
slave.
Slave devices on this network will only
produce a receive interrupt when a frame
is received with the MPB set,so the
interrupt handler can check the address
which has been transmitted.
* This feature allows to connect SPI compliant peripherals in most cases.
H8/300H H8S H8S/21xx
Smart card interface H8/3048 series Yes No
(ISO 7816)
Multi-processor mode Yes Yes Yes
IIC No H8S/2238 H8S/21x7,8
H8S/2633
IrDA No H8S/2633 Yes
LSB/MSB-first selectable* No Yes Yes
No. of SCI with 1 min. 2 No
DMA support
DTC support No Yes H8S/21x7,8
This form of communication has many
uses in microcontroller applications,such
as inter-device communications,
diagnostics,host communication or as an
interface to peripherals. All of Hitachi’s
16-bit microcontrollers have at least one
SCI,even though most have two or
more. The SCI’s on H8/300H and H8S
can operate in asynchronous (‘UART’)
or synchronous mode.
They have independent baud rate
generators, so that none of the general
purpose timers is used up to generate
transmit/receive clocks,and external
clocking is also possible. They are double
buffered to allow ‘back-to-back’
transmission. Break detection is possible
by reading the RxD pin level after a
framing error has been detected.
To allow efficient SCI service by
interrupt service routines each SCI is
provided with 4 different interrupts, each
with its own interrupt vector. These are
transmit-data-empty, transmit-end,
receive-data-full and receive error.
Receive data errors are trapped using
three error conditions -overflow, framing
and parity. These three errors are
indicated via one interrupt vector and
three status flags in the serial status
register.
Some other capabilities vary from family
to family, as shown in the table.
The maximum bit rate in asynchronous
operation is 625kbit/s at 20MHz for
H8/300H and 781kbit/s at 25MHz for
H8S,using the internal BRR. Using
external clocks the values for
asynchronous mode are half of that. For
synchronous operation with external
clock the bit rate is 3.33Mbit/s at
Transmitting
station
Receiving
station A
(ID= 01)
Receiving
station B
(ID= 02)
Receiving
station C
(ID= 03)
Receiving
station D
(ID= 04)
Serial transmission line
Serial
data
ID transmission cycle=
receiving station
specification
Data transmission cycle=
Data transmission to
receiving station specified by ID
(MPB= 1) (MPB= 0)
H'01
H'AA
Legend MPB: Multiprocessor bit
Figure 19