Specifications

31
H8/3039
P7
7
/AN
7
P7
6
/AN
6
P7
5
/AN
5
P7
4
/AN
4
P7
3
/AN
3
P7
2
/AN
2
P7
1
/AN
1
P7
0
/AN
0
AV
CC
AV
SS
PA
7
/TP
7
/TIOCB
2
/A
20
PA
6
/TP
6
/TIOCA
2
/A
21
PA
5
/TP
5
/TIOCB
1
/A
22
PA
4
/TP
4
/TIOCA
1
/A
23
PA
3
/TP
3
/TIOCB
0
/TCLKD
PA
2
/TP
2
/TIOCA
0
/TCLKC
PA
1
/TP
1
/TCLKB
PA
0
/TP
0
/TCLKA
PB
7
/TP
15
/ADTRG
PB
5
/TP
13
/TOCXB
4
PB
4
/TP
12
/TOCXA
4
PB
3
/TP
11
/TIOCB
4
PB
2
/TP
10
/TIOCA
4
PB
1
/TP
9
/TIOCB
3
PB
0
/TP
8
/TIOCA
3
P2
7
/A
15
P2
6
/A
14
P2
5
/A
13
P2
4
/A
12
P2
3
/A
11
P2
2
/A
10
P2
1
/A
9
P2
0
/A
8
P1
7
/A
7
P1
6
/A
6
P1
5
/A
5
P1
4
/A
4
P1
3
/A
3
P1
2
/A
2
P1
1
/A
1
P1
0
/A
0
P9
5
/SCK
1
/IRQ
5
P9
4
/SCK
0
/IRQ
4
P9
3
/RxD
1
P9
2
/RxD
0
P9
1
/TxD
1
P9
0
/TxD
0
P5
3
/A
19
P5
2
/A
18
P5
1
/A
17
P5
0
/A
16
Data bus (lower)
Bus
controller
Clock osc.
H8/300H CPU
ROM
(Flash memory,
masked ROM)
RAM
16-bit
integrated
timer unit
(ITU)
Programmable
timing pattern
controller (TPC)
Interrupt
controller
Serial
communication
interface
(SCI) x 2 channels
Watchdog
timer
(WDT)
A/D converter
Port 3
P6
5
/WR
P6
4
/RD
P6
3
/AS
P6
0
/WAIT
P8
1
/IRQ
1
P8
0
/IRQ
0
MD
1
MD
0
EXTAL
XTAL
ø
STBY
RES
RESO/FWE*
NMI
V
CC
V
CC
V
SS
V
SS
V
SS
P3
7
/D
7
P3
6
/D
6
P3
5
/D
5
P3
4
/D
4
P3
3
/D
3
P3
2
/D
2
P3
1
/D
1
P3
0
/D
0
Port 2Port 1
Port 5
Port 9
Port 7Port APort B
Note:
* Masked ROM : RESO
Flash memory: FWE
Port 8 Port 6
Address bus
Data bus (upper)
MD2
V V V V V V V V V
CC CC CC SS SS SS SS SS SS
P3 /D P3 /D P3 /D P3 /D P3 /D P3 /D P3 /D P3 /D
7 6 5 4 3 2 1 0
P4 /D P4 /D P4 /D P4 /D P4 /D P4 /D P4 /D P4 /D
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
Port 3 Port 4
Port 5Port 9
P5 /A
P5 /A
P5 /A
P5 /A
3
2
1
0
19
18
17
16
P2 /A
P2 /A
P2 /A
P2 /A
P2 /A
P2 /A
P2 /A
P2 /A
7
6
5
4
3
2
1
0
P9 /SCK /IRQ
P9 /SCK /IRQ
P9 /RxD
P9 /RxD
P9 /TxD
P9 /TxD
5
4
3
2
1
0
1
0
1
0
1
0
5
4
DA
1
/AN
7
/P7
7
DA
0
/AN
6
/P7
6
AN
5
/P7
5
AN
4
/P7
4
AN
3
/P7
3
AN
2
/P7
2
AN
1
/P7
1
AN
0
/P7
0
Port 7
A
20
/TIOCB
2
/TP
7
/PA
7
A
21
/TIOCA
2
/TP
6
/PA
6
A
22
/TIOCB
1
/TP
5
/PA
5
A
23
/TIOCA
1
/TP
4
/PA
4
TCLKD/TIOCB
0
/TP
3
/PA
3
TCLKC/TIOCA
0
/TP
2
/PA
2
TEND
1
/TCLKB/TP
1
/PA
1
TEND
0
/TCLKA/TP
0
/PA
0
Port A
RxD
2
/TP
15
/PB
7
TxD
2
/TP
14
/PB
6
SCK
2
/LCAS/TP
13
/PB
5
UCAS/TP
12
/PB
4
CS
4
/DREQ
1
/TMIO
3
/TP
11
/PB
3
CS
5
/TMO
2
/TP
10
/PB
2
CS
6
/DREQ
0
/TMIO
1
/TP
9
/PB
1
CS
7
/TMO
0
/TP
8
/PB
0
Port 8
CS
0
/P8
4
ADTRG/CS
1
/IRQ
3
/P8
3
CS
2
/IRQ
2
/P8
2
CS
3
/IRQ
1
/P8
1
RFSH/IRQ
0
/P8
0
MD
MD
MD
EXTAL
XTAL
STBY
RES
FWE*/RESO
NMI
2
1
0
H8/300H CPU
Clock pulse
generator
Interrupt controller
ROM
(mask ROM or
flash memory)
DMA controller
(DMAC)
Serial communication
interface
(SCI) 3 channels
×
Watchdog timer
(WDT)
15 14 13 12 11 10 9 8
Address bus
Data bus (upper)
Data bus (lower)
15
14
13
12
11
10
9
8
Port 2
P1 /A
P1 /A
P1 /A
P1 /A
P1 /A
P1 /A
P1 /A
P1 /A
7
6
5
4
3
2
1
0
Port 1
7
6
5
4
3
2
1
0
φ/P6
7
LWR/P6
6
HWR/P6
5
RD/P6
4
AS/P6
3
BACK/P6
2
BREQ/P6
1
WAIT/P6
0
RAM
16-bit timer unit
8-bit timer unit
A/D converter
D/A converter
Port 6
Bus controller
Programmable
timing pattern
controller (TPC)
Port B
V
REF
AV
CC
AV
SS
Note:
*Functions as RESO in the mask
ROM versions and as FWE in the
flash memory version.
H8/3067
Lowest cost H8/300H with Flash
■ ROM 16k-128k, RAM 512Byte-
4k, 128K Flash
■ 18MHz clock yields 111ns min.
instruction
■ pin compatible with other
H8/303x, but with 2x SCI
■ popular ITU timer unit with AC
motor drive modes
■ Ideal for many industrial
applications
Enhanced successor of popular
H8/3048
■ nearly pin compatible with
H8/3048
■ single voltage Flash requires no
Vpp
■ 20MHz clock for 20% higher
performance
■ now 3x USART, modified timers
without AC motor drive modes
■ Lower cost variant H8/3062
without DMA and with 2x SCI
■ please refer to application note
APPS/072/1.0