Specifications

7
Addressing
To support large memory systems,the
linear address space of the H8/300H and
the H8S CPU core allows direct access
to every address in the whole 16MByte
address space via 24-bit address pointers.
The linear address space means there is
no need to set up page registers and
there are also no limitations on the size
of code modules or data arrays and
structures.
Addressing
Modes
Another way a CPU architecture can
support the efficiency of the compiler is
by providing a full set of powerful and
flexible addressing modes. To ensure that
the compiler is as efficient as possible the
H8S and H8/300H CPU’s provide eight
addressing modes as shown in the table.
Each instruction can use a subset of the
Register contents
23 031 0
Register indirect with post-increment or pre-decrement
*Register indirect with post-increment @ERn+
Operand Size Added Value
Byte
Word
Longword
1
2
4
op reg
1, 2 or 4
Register contents
23 0
31 0
*Register indirect with pre-increment @ERn
op reg
1, 2 or 4
available addressing modes. Supporting
both,array and stack data types,the CPU
has indirect addressing with either
postincrement or predecrement. These
modes support byte, word and long word
data (±1,2 and 4) as shown in figure 7.
Three absolute addressing modes are
provided using 8, 16 or 24-bit absolute
addresses. Using the 24-bit address the
entire 16MBytes address space is
accessible. The 8 and 16-bit absolute
address modes assume that the upper
byte or word of the address is H’FFFF or
H’FF respectively. This allows for the
efficient address specification for the on-
chip I/O area and RAM areas which are
both placed at the top of the address
map. These shortened addresses save
significant amounts of code when these
areas are accessed.
Register direct R n
Register indirect @ E R n
Register indirect @ (d:16, E R n)
with displacement @ (d:24, E R n)
Register indirect with post-increment/ @ E R n +, @ - E R n
Register indirect with pre-decrement
Absolute address @ a a :8, @ a a :16, @ a a :24
Immediate # x x :8, # x x :16, # x x :32
PC-relative @ (d :8, PC), @ (d : 16, PC)
Memory indirect @@ a a :8
Bit Processing
In microcontroller applications it is often
necessary to manipulate data on a bit by
bit basis. A good example would be
where an I/O pin needs to be set to
switch on a lamp or a solenoid. To meet
this demand H8S and H8/300H have 14
separate bit processing instructions which
allow the programmer to manipulate bit
data very easily.
It is also possible to perform boolean
algebra on bit data using the carry flag of
the CCR register as a bit accumulator. In
a microcontroller application it is often
necessary to perform a branch depending
on the values of two bit flags located in
RAM or I/O ports. Using the boolean
operations provided by H8S and
H8/300H the first bit can be loaded into
the carry flag. Then a bitwise logical
operation can be executed using the
second bit. This sequence would then be
followed by a branch depending on the
value of the carry flag.
Another feature of the H8S and H8/300H
bit processing capability is its ability to
access bits indirectly, using the value from
a general purpose register as a bit pointer.
This mechanism is shown in figure 6 and
is useful for scanning a byte for set or
cleared bits.
Software Interrupt
The TRAPA instruction has been
implemented in the H8S and H8/300H
CPU. This instruction implements a
software interrupt, jumping to a service
routine via one of four exception vectors
(TRAPA 0 - 3). This operation can be
used to implement fast, space efficient
calls to often used sub-routines such as
schedulers and other O/S routines. The
TRAPA instruction can also be used as a
call to an error handling routine.
Figure 7