Power Supply Specification Sheet

ManualsBrandsRenesas ManualsPower SupplyHD49335HNP

Rev.1.0, Feb.12.2004, page 1 of 29

HD49335NP/HNP

CDS/PGA & 10-bit A/D TG Converter

REJ03F0097-0100Z

Rev.1.0

Feb.12.2004

Description

The HD49335NP/HNP is a CMOS IC that provides CDS-PGA analog processing (CDS/PGA) suitable for CCD camera

digital signal processing systems together with a 10-bit A/D converter and timing generator in a single chip.

There are address map and timing generator charts besides this specification. May be contacted to our sales department

if examining the details.

Functions

• Correlated double sampling

• PGA

• Serial interface control

• 10-bit ADC

• Timing generator

• Operates using only the 3 V voltage

• Corresponds to switching mode of power dissipation and operating frequency

Power dissipation: 220 mW (Typ), maximum frequency: 36 MHz (HD49335HNP)

Power dissipation: 150 mW (Typ), maximum frequency: 25 MHz (HD49335NP)

• ADC direct input mode

• QFN 64-pin package

Features

• Suppresses low-frequency noise, which output from CCD by the correlated double sampling.

• The S/H response frequency characteristics for the reference level can be adjusted using values of external parts and

registers.

• High sensitivity is achieved due to the high S/N ratio and a wide dynamic range provided by a PG amplifier.

• PGA, pulse timing, standby mode, etc., is achieved via a serial interface.

• High precision is provided by a 10-bit-resolution A/D converter.

• Difference encoded gray code can be selected as an A/D output code. It is effective in suppression of solarization

(wave pattern). It is patented by Renesas.

• Timing generator generates the all of pulse which are needed for CCD driving.

Summary of content (30 pages)

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HD49335NP/HNP CDS/PGA & 10-bit A/D TG Converter REJ03F0097-0100Z Rev.1.0 Feb.12.2004 Description The HD49335NP/HNP is a CMOS IC that provides CDS-PGA analog processing (CDS/PGA) suitable for CCD camera digital signal processing systems together with a 10-bit A/D converter and timing generator in a single chip. There are address map and timing generator charts besides this specification. May be contacted to our sales department if examining the details.
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HD49335NP/HNP VRM VRT VRB BIAS ADC_in AVSS DVSS3 STROB SUB_PD SUB_SW XSUB CH4 CH3 CH2 CH1 XV4 Pin Arrangement 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 49 31 50 30 51 29 52 28 53 27 54 26 55 25 56 24 57 23 58 22 59 21 60 20 61 19 62 18 63 17 64 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 XV3 XV2 XV1 DVDD3 DVDD4 1/4clk_o H2A DVSS4 DVSS4 1/2clk_o H1A DVDD4 DVDD3 RG Reset VD_in ID DVSS1,2 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DVDD2 DVSS3 CLK_in HD_in AVDD BLKC CDS_in AVDD BLKFB BLKSH AVSS Test2 Test1 DLL_C D
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HD49335NP/HNP Pin Description (cont.) Pin No. Symbol Description I/O Analog(A) or Digital(D) 30 XV1 V.CCD transfer pulse output-1 O D 2 mA/10 pF 31 XV2 V.CCD transfer pulse output-2 O D 2 mA/10 pF 32 XV3 V.CCD transfer pulse output-3 O D 2 mA/10 pF 33 XV4 V.
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HD49335NP/HNP Input/Output Equivalent Circuit Pin Name Digital output Equivalent Circuit D0 to D9, HD_in, VD_in, H1A, H2A, 1/2clk_o, 1/4clk_o, 41cont, SUB_SW, SUB_PD DVDD DIN Digital output ENABLE DVDD ID, RG, MON, XV1 to XV4, CH1 to CH4, XSUB Digital output DIN Digital input DVDD CLK_in, HD_in, VD_in, ADCLK, OBP, SPBLK, SPSIG, CS, SCK, SDATA, PBLK, OEB, Reset, Test1, Test2, SUB_SW, STROB Digital input *1 Note: Only OEB is pulled down to about 70 kΩ.
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HD49335NP/HNP SUB_SW SUB_PD AVSS Timing generator DLL DVSS1 to 4 STROB SP1 SP2 ADCLK OBP CPDM PBLK Reset ADC_in BLKSH D9 D8 CDS 10bit ADC PGA Output latch circuit CDS_in BLKC BLKFB DVDD1 to 4 AVDD CLK_in HD_in VD_in RG H1A 1/2clk_o H2A 1/4clk_o XV1 XV2 XV3 XV4 CH1 CH2 CH3 CH4 XSUB Block Diagram DC offset compensation circuit Serial interface Bias generator D7 D6 D5 D4 D3 D2 D1 Rev.1.0, Feb.12.
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HD49335NP/HNP Internal Functions Functional Description • CDS input  CCD low-frequency noise is suppressed by CDS (correlated double sampling).  The signal level is clamped at 14 LSB to 76 LSB by resister during the OB period. *1  Gain can be adjusted using 8 bits of register (0.132 dB steps) within the range from –2.36 dB to 31.40 dB. *2 • ADC input  The center level of the input signal is clamped at 512 LSB (Typ).  Gain can be adjusted using 8 bits of register (0.
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HD49335NP/HNP 3. Automatic Offset Calibration Function and Black-Level Clamp Data Settings The DAC DC voltage added to the output of the PGA amplifier is adjusted by automatic offset calibration. The data, which cancels the output offset of the PGA amplifier and the input offset of the ADC, and the clamp data (14 LSB to 76 LSB) set by register are added and input to the DAC.
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HD49335NP/HNP PBLK MINV X L LINV TEST0 H L TEST1 STBY 6. ADC Digital Output Control Function The ADC digital output includes the functions output enable, code conversion, and test mode. Tables 3, 4 and 5 show the output functions and the codes. Table 3 ADC Digital Output Functions D9 D8 ADC Digital Output D7 D6 D5 D4 X X X Hi-Z L L L Same as in table 4. L H L D9 is inverted in table 4. H L L D8 to D0 are inverted in table 4. H H L D9 to D0 are inverted in table 4.
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HD49335NP/HNP 7. Adjustment of Black-Level S/H Response Frequency Characteristics The CR time constant that is used for sampling/hold (S/H) at the black level can be adjusted by changing the register settings, as shown in table 6.
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HD49335NP/HNP Timing Chart Figure 2 shows the timing chart when CDSIN and ADCIN input modes are used.
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HD49335NP/HNP Detailed Timing Specifications Detailed Timing Specifications when CDSIN Input Mode is Used Figure 3 shows the detailed timing specifications when the CDSIN input mode is used, and table 8 shows each timing specification. Black level Signal level CDS_in (2) (3) (1) SP1 Vth (5) (4) SP2 Vth (6) (7) (8) ADCLK Vth (9) (10) D0 to D9 (11) (12) (13) H1 Figure 3 Detailed Timing Chart when CDSIN Input Mode is Used Table 8 No.
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HD49335NP/HNP Detailed Timing Specifications at Pre-Blanking Figure 5 shows the pre-blanking detailed timing specifications. PBLK Vth VOH Digital output (D0 to D9) ADC data ADC data Clamp Level VOL ADCLK × 2 clock ADCLK × 10 clock Figure 5 Detailed Timing Specifications at Pre-Blanking Detailed Timing Specifications when ADCIN Input Mode is Used Figure 6 shows the detailed timing chart when ADCIN input mode is used, and table 9 shows each timing specification.
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HD49335NP/HNP Dummy Clamp It adjusts the mis-clamp which occurs when taking the photo under the highlight conditions. (Like a sun) Normally it woks with the OB clamp, however when black level is out of the range caused by hightlight enter to OB part, it changes to clamp processing by dummy bit level. Resister settings are follows.
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HD49335NP/HNP Absolute Maximum Ratings (Ta = 25°C) Item Symbol Ratings Unit Power supply voltage Analog input voltage VDD VIN 4.1 –0.3 to AVDD +0.3 V V Digital input voltage Operating temperature range VI Ta –0.3 to DVDD +0.3 –10 to +75 V °C Power dissipation Storage temperature Pt Tstg 750 –55 to +125 mW °C Power supply voltage Vopr 2.70 to 3.30 V Note: AVDD, AVSS are analog power source systems of CDS, PGA, and ADC. DVDD1, DVSS1 are digital power source systems of CDS, PGA and ADC.
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HD49335NP/HNP Electrical Characteristics (cont.) (Unless othewide specified, Ta = 25°C, AVDD = 3.0 V, DVDD = 3.0 V, and RBIAS = 33 kΩ) • Items for CDSIN Input Mode Item Symbol Min Typ Max Unit Test Conditions Remarks Consumption current (1) IDD1 — 84 96.6 mA fCLK = 36 MHz CDSIN mode LoPwr = low Consumption current (2) IDD2 — 58 66.7 mA fCLK = 20 MHz CDSIN mode LoPwr = high CCD offset tolerance range VCCD (–100) — (100) mV Timing specifications (1) tCDS1 — (1.
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HD49335NP/HNP Electrical Characteristics (cont.) (Unless othewide specified, Ta = 25°C, AVDD = 3.0 V, DVDD = 3.0 V, and RBIAS = 33 kΩ) • Items for ADCIN Input Mode Item Symbol Min Typ Max Unit Test Conditions Remarks Consumption current (3) IDD3 — 32 38.4 mA fCLK = 36 MHz ADCIN mode LoPwr = low Consumption current (4) IDD4 — 22 27.5 mA fCLK = 25 MHz ADCIN mode LoPwr = high Timing specifications (14) tADC1 — (6) — ns Timing specifications (15) tADC2 Typ × 0.
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HD49335NP/HNP Serial Interface Specifications Timing Specifications Data is determined at CS rising edge tINT2 tINT1 Latches SDATA at SCK rising edge CS fSCK SCK tsu SDATA tho D8 D9 D10 D11 D12 D13 D14 D15 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 STD2(Upper data) STD1(Lower data) address(address) Figure 8 Serial Interface Timing Specifications Item Min Max fSCK tINT1,2 — 50 ns 5 MHz — tsu tho 50 ns 50 ns — — Notes: 1. 2. 3. 4. 5. 3 byte continuous communications.
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HD49335NP/HNP Explanation of Serial Data of CDS Part Serial data of CDS part are assigned to address H’F0 to H’F8. Functions are follows. 1 1 1 Address 1 0 0 0 0 STD1[7:0] (L) STD2[15:8] (H) D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 PGA gain test_I1 • PGA gain (D0 to D7 of address H’F0) Details are referred to page 5 block diagram. At CDS_in mode: –2.36 dB + 0.132 dB × N (Log linear) At ADC_in mode: 0.57 times + 0.
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HD49335NP/HNP • Output mode (D2 to D4 of address H’F1 and address H’F4 of D6) It is a test mode. Combination details are table 3 to 5. Normally set to all 0. • SHA-fsel (D8 to D9 of address H’F1) It is a LPF switching of SH amplifier. Frequency characteristics are referred to page 8. To get rough idea, set the double cut off frequency point with using. • SHSW-fsel (D10 to D13 of address H’F1) It is a time constant which sampling the black level of SH amplifier.
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HD49335NP/HNP 1 1 1 Address 1 0 1 0 STD1[7:0] (L) D7 D6 D5 D4 D3 D2 D1 D0 0 VD latch H12_Buff MON • MON (D0 to D2 of address H’F4) Select the pulse which output to pin MON (pin 60). When D0 to D2: 0, Fix to Low When 1, ADCLK When 2, SP1 When 3, SP2 When 4, OBP When 5, PBLK When 6, CPDM When 7, DLL_test • H12Baff (D3 to D6 of address H’F4) Select the buffer size which output to pin H1A, H2A (pin 22, 26).
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HD49335NP/HNP Ripple (pseudo outline made by quantized error) occurres on the point which swithing the ADC output multiple bit in parallel. When switching the several of ADC output at the same time, ripple (pseudo outline caused by miss quantization) occurs to the image. Differential code and gray code are recommended for this countermeasure. Figure 10 indicates circuit block.
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HD49335NP/HNP • Address H’F5 sets the DLL delay time and selects the 1/4 phase. Details are on the next page. And D15 of address H’F8 can switch 2/3 divided mode but ensure that this address data relative to valid/invalid.
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HD49335NP/HNP (3) Setting method of DLL 1. DLL step decides the how many divide the 1 cycle of sensor CLK. For reference, set 1 ns(when 2 ns DLL_current bit = 0, ADCLK(0) when 1 set to 1 ns) (In phase with H1) Can be set 16 to 64 steps by 4 steps. Steps = 4 + (4 × N); possible to set N = 3 to 15 Recommended steps is clk_in = when 11 to 14 MHz: H'0E(60 steps) when 14 to 22MHz: H'09(40 steps) when 22 to 50MHz: H'1E(60 steps) P_ADCLK when 50 to 72MHz: H'19(40 steps) 2.
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HD49335NP/HNP Operation Sequence at Power On Must be stable within the operating power supply voltage range VDD CLK_in 3clk or more Hardware Reset Note: At 2 divided mode: ADCLK = 1/2CLK_in At 3 divided mode: ADCLK = 1/3CLK_in 6clk or more HD49335 serial data transfer 2ms or more (Charge of external C) (1) (2) (3) 40,000ADCLK or more (offset calibration) (5) (4) SP1 Start control SP2 ADCLK of TG and camera DSP OBP etc.
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HD49335NP/HNP Timing Specifications of High Speed Pulse • H1, H2, RG waveform tr twh tf H2 90% 50% 10% H1 two tr twh twl tf tH1DL 90% 50% 10% RG twl twh twl tr tf Load Unit capacitance min typ max min typ max min typ max min typ max H1/H2 14 20 — 14 20 — — 8.0 14 — 8.0 14 ns 165 pF RG 7 10 — — 37 — — 4.0 — — 4.
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HD49335NP/HNP Notice for Use 1. Careful handling is necessary to prevent damage due to static electricity. 2. This product has been developed for consumer applications, and should not be used in non-consumer applications. 3. As this IC is sensitive to power line noise, the ground impedance should be kept as small as possible. Also, to prevent latchup, a ceramic capacitor of 0.1 µF or more and an electrolytic capacitor of 10 µF or more should be inserted between the ground and power supply. 4.
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HD49335NP/HNP Example of Recommended External Circuit Pin 57 • Slave mode Pin 57(Test1 = Low) to CCD 47µ 3.0V 47µ 47/6 + Specification Mode Low Slave mode CLK, HD, VD input from SSG. Hi Master mode HD, VD output ∗ Pin 56 = Low: TESTIN mode. Please do not use. Reset(Normally Hi) 0.1 0.1 33 XV4 to V.
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HD49335NP/HNP • CDS single operating mode Pin 56(Test2 = Low) ∗Pin 57 is "Don't care" in this mode. 47µ 3.0V + 47/6 47µ Reset(Normally Hi) 0.1 0.1 Reset DVDD4 DVDD3 33 DVSS4 DVSS4 DVDD3 DVDD4 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 34 15 DVSS3 DVDD2 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 DVSS1,2 35 36 PBLK 37 OBP 38 CP_DM 39 ADCK 40 SP2 HD49335 41 SP1 42 DVSS3 43 AVSS 33k 45 BIAS 0.1 46 VRB 0.1 47 VRT 0.
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HD49335NP/HNP Package Dimensions Unit: mm 9.00 ± 0.1 8.80 C Part A (0 0 .2 ) ) .1 6 (0 2 .8 0.50 ) 0.65 .2) (φ0 (3 C0.50 Index 1 8.80 9.00 ± 0.1 B 0.65 A 9 0.40 ± 0.1 0.20 ± 0.05 0.05 M S A-B C S 10 0. C 0.20 ± 0.05 0.80 Max 0.05 S 0.40 ± 0.1 Enlargement of Part A Rev.1.0, Feb.12.2004, page 29 of 29 Package Code JEDEC JEITA Mass (reference value) TNP-64AV — — 0.
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Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage.