Datasheet

Section 6 Power-Down Modes
Rev. 6.00 Mar. 24, 2006 Page 85 of 412
REJ09B0142-0600
Bit Bit Name
Initial
Value R/W Description
3 NESEL 0 R/W Noise Elimination Sampling Frequency Select
The subclock pulse generator generates the watch
clock signal (φ
W
) and the system clock pulse generator
generates the oscillator clock (φ
OSC
). This bit selects the
sampling frequency of the oscillator clock when the
watch clock signal (φ
W
) is sampled. When φ
OSC
= 4 to 16
MHz, clear NESEL to 0.
0: Sampling rate is φ
OSC
/16
1: Sampling rate is φ
OSC
/4
2
1
0



0
0
0



Reserved
These bits are always read as 0.
Table 6.1 Operating Frequency and Waiting Time
STS2 STS1 STS0 Waiting Time 16 MHz 10 MHz 8 MHz 4 MHz 2 MHz 1 MHz 0.5 MHz
0 0 0 8,192 states 0.5 0.8 1.0 2.0 4.1 8.1 16.4
1 16,384 states 1.0 1.6 2.0 4.1 8.2 16.4 32.8
1 0 32,768 states 2.0 3.3 4.1 8.2 16.4 32.8 65.5
1 65,536 states 4.1 6.6 8.2 16.4 32.8 65.5 131.1
1 0 0 131,072 states 8.2 13.1 16.4 32.8 65.5 131.1 262.1
1 1,024 states 0.06 0.10 0.13 0.26 0.51 1.02 2.05
1 0 128 states 0.00 0.01 0.02 0.03 0.06 0.13 0.26
1 16 states 0.00 0.00 0.00 0.00 0.01 0.02 0.03
Note: Time unit is ms.