Datasheet

Rev.5.00 Nov. 02, 2005 Page xi of xxxii
3.2.5 Interrupt Flag Register 1 (IRR1)............................................................................. 53
3.2.6 Interrupt Flag Register 2 (IRR2)............................................................................. 55
3.2.7 Wakeup Interrupt Flag Register (IWPR) ................................................................ 55
3.3 Reset Exception Handling.................................................................................................... 57
3.4 Interrupt Exception Handling............................................................................................... 57
3.4.1 External Interrupts .................................................................................................. 57
3.4.2 Internal Interrupts ...................................................................................................59
3.4.3 Interrupt Handling Sequence .................................................................................. 59
3.4.4 Interrupt Response Time......................................................................................... 60
3.5 Usage Notes......................................................................................................................... 62
3.5.1 Interrupts after Reset............................................................................................... 62
3.5.2 Notes on Stack Area Use ........................................................................................ 62
3.5.3 Notes on Rewriting Port Mode Registers ...............................................................62
Section 4 Address Break......................................................................................63
4.1 Register Descriptions...........................................................................................................63
4.1.1 Address Break Control Register (ABRKCR) .........................................................64
4.1.2 Address Break Status Register (ABRKSR) ............................................................ 65
4.1.3 Break Address Registers (BARH, BARL).............................................................. 65
4.1.4 Break Data Registers (BDRH, BDRL) ................................................................... 66
4.2 Operation ............................................................................................................................. 66
Section 5 Clock Pulse Generators........................................................................69
5.1 System Clock Generator ...................................................................................................... 70
5.1.1 Connecting Crystal Resonator ................................................................................ 70
5.1.2 Connecting Ceramic Resonator .............................................................................. 71
5.1.3 External Clock Input Method.................................................................................. 71
5.2 Subclock Generator..............................................................................................................72
5.2.1 Connecting 32.768-kHz Crystal Resonator............................................................. 72
5.2.2 Pin Connection when Not Using Subclock............................................................. 73
5.3 Prescalers ............................................................................................................................. 73
5.3.1 Prescaler S .............................................................................................................. 73
5.3.2 Prescaler W............................................................................................................. 73
5.4 Usage Notes......................................................................................................................... 74
5.4.1 Note on Resonators................................................................................................. 74
5.4.2 Notes on Board Design........................................................................................... 74
Section 6 Power-Down Modes ............................................................................75
6.1 Register Descriptions...........................................................................................................75
6.1.1 System Control Register 1 (SYSCR1).................................................................... 76