Datasheet

Section 13 Timer Z
Rev.5.00 Nov. 02, 2005 Page 183 of 500
REJ09B0027-0500
13.3.2 Timer Mode Register (TMDR)
TMDR selects buffer operation settings and synchronized operation.
Bit Bit Name
Initial
Value R/W Description
7 BFD1 0 R/W Buffer Operation D1
0: GRD_1 operates normally
1: GRB_1 and GRD_1 are used together for buffer
operation
6 BFC1 0 R/W Buffer Operation C1
0: GRC_1 operates normally
1: GRA_1 and GRD_1 are used together for buffer
operation
5 BFD0 0 R/W Buffer Operation D0
0: GRD_0 operates normally
1: GRB_0 and GRD_0 are used together for buffer
operation
4 BFC0 0 R/W Buffer Operation C0
0: GRC_0 operates normally
1: GRA_0 and GRC_0 are used together for buffer
operation
3 to 1  All 1  Reserved
These bits are always read as 1, and cannot be modified.
0 SYNC 0 R/W Timer Synchronization
0: TCNT_1 and TCNT_0 operate as a different timer
1: TCNT_1 and TCNT_0 are synchronized
TCNT_1 and TCNT_0 can be pre-set or cleared
synchronously