Datasheet

Section 13 Timer Z
Rev.5.00 Nov. 02, 2005 Page 197 of 500
REJ09B0027-0500
13.3.13 PWM Mode Output Level Control Register (POCR)
POCR control the active level in PWM mode. Timer Z has two POCR registers, one for each
channel.
Bit Bit Name
Initial
value R/W Description
7 to 3  All 1  Reserved
These bits are always read as 1.
2 POLD 0 R/W PWM Mode Output Level Control D
0: The output level of FTIOD is low-active
1: The output level of FTIOD is high-active
1 POLC 0 R/W PWM Mode Output Level Control C
0: The output level of FTIOC is low-active
1: The output level of FTIOC is high-active
0 POLB 0 R/W PWM Mode Output Level Control B
0: The output level of FTIOB is low-active
1: The output level of FTIOB is high-active
13.3.14 Interface with CPU
1. 16-bit register
TCNT and GR are 16-bit registers. Reading/writing in a 16-bit unit is enabled but disabled in
an 8-bit unit since the data bus with the CPU is 16-bit width. These registers must always be
accessed in a 16-bit unit. Figure 13.5 shows an example of accessing the 16-bit registers.
H
Internal data bus
Bus interface
Module data bus
C
P
U
L
TCNTLTCNTH
Figure 13.5 Accessing Operation of 16-Bit Register (between CPU and TCNT (16 bits))