Datasheet

Section 13 Timer Z
Rev.5.00 Nov. 02, 2005 Page 242 of 500
REJ09B0027-0500
13.5.2 Status Flag Clearing Timing
The status flag can be cleared by writing 0 after reading 1 from the CPU. Figure 13.51 shows the
timing in this case.
Address TSR address
φ
WTSR
(internal write signal)
IMF, OVF
ITMZ
Figure 13.51 Status Flag Clearing Timing
13.6 Usage Notes
1. Contention between TCNT Write and Clear Operations: If a counter clear signal is generated
in the T
2
state of a TCNT write cycle, TCNT clearing has priority and the TCNT write is not
performed. Figure 13.52 shows the timing in this case.
T 1 T 2
TCNT
TCNT write cycle
TCNT address
WTCNT
(internal write signal)
Clearing has priority.
Counter clear signal
N H'0000
φ
Figure 13.52 Contention between TCNT Write and Clear Operations