Datasheet

Section 13 Timer Z
Rev.5.00 Nov. 02, 2005 Page 244 of 500
REJ09B0027-0500
3. Contention between GR Write and Compare Match: If a compare match occurs in the T
2
state
of a GR write cycle, GR write has priority and the compare match signal is disabled. Figure
13.54 shows the timing in this case.
T1 T2
GR N M
TCNT
GR write cycle
GR address
WGR
(internal write signal)
GR write data
Compare match
signal
Disabled
N N+1
φ
Figure 13.54 Contention between GR Write and Compare Match