Datasheet

Section 17 I
2
C Bus Interface 2 (IIC2)
Rev.5.00 Nov. 02, 2005 Page 326 of 500
REJ09B0027-0500
3. Read ICDRR every time RDRF is set. If 8th receive clock pulse falls while RDRF is 1, SCL is
fixed low until ICDRR is read. The change of the acknowledge before reading ICDRR, to be
returned to the master device, is reflected to the next transmit frame.
4. The last byte data is read by reading ICDRR.
ICDRS
ICDRR
12 1345678 99
A
A
RDRF
Data 1 Data 2
Data 1
SCL
(Master output)
SDA
(Master output)
SDA
(Slave output)
SCL
(Slave output)
Bit 7 Bit 7Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
[2] Read ICDRR (dummy read)
[2] Read ICDRR
User
processing
Figure 17.11 Slave Receive Mode Operation Timing (1)
ICDRS
ICDRR
12345678 99
A
A
RDRF
SCL
(Master output)
SDA
(Master output)
SDA
(Slave output)
SCL
(Slave output)
User
processing
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Data 1
[3] Set ACKBT
[3] Read ICDRR
[4] Read ICDRR
Data 2
Data 1
Figure 17.12 Slave Receive Mode Operation Timing (2)