Datasheet

Section 1 Overview
Rev.5.00 Nov. 02, 2005 Page 4 of 500
REJ09B0027-0500
P10/TMOW
P11/PWM
P12
P14/IRQ0
P15/IRQ1/TMIB1
P16/IRQ2
P17/IRQ3/TRGV
P57/SCL
P56/SDA
P55/WKP5/ADTRG
P54/WKP4
P53/WKP3
P52/WKP2
P51/WKP1
P50/WKP0
PB0/AN0 PB1/AN1 PB2/AN2 PB3/AN3 PB4/AN4 PB5/AN5 PB6/AN6 PB7/AN7
V
CL
V
CC
V
SS
RES TEST NMI
AV CC
P20/SCK3
P21/RXD
P22/TXD
P23
P24
P87
P86
P85
OSC1 OSC2 X1 X2
CPU
H8/300H
Data bus (lower)
System
clock
generator
Subclock
generator
ROM
14-bit
PWM
Timer Z
Timer V
A/D converter
The HD64N3687G is a stacked-structure product in which an EEPROM chip is mounted on the HD64F3687G (F-ZTAT
TM
version).
The HD6483687G is a stacked-structure product in which an EEPROM chip is mounted on the HD6433687G (mask-ROM version).
Note:
RAM
RTC
SCI3
SCI3_2
Watchdog
timer
IIC2
P67/FTIOD1
P66/FTIOC1
P65/FTIOB1
P64/FTIOA1
P63/FTIOD0
P62/FTIOC0
P61/FTIOB0
P60/FTIOA0
P76/TMOV
P75/TMCIV
P74/TMRIV
P72/TXD_2
P71/RXD_2
P70/SCK3_2
P30
P31
P32
P33
P34
P35
P36
P37
Data bus (upper)
Address bus
Port B
Port 8I
2
C bus Port 7 Port 6
Port 1Port 2Port 3Port 5
Timer B1
POR/LVD
(optional)
SDA
SCL
EEPROM
Address bus
Address bus
Figure 1.2 Internal Block Diagram of H8/3687N (EEPROM Stacked Version)