Datasheet

Section 22 List of Registers
Rev.5.00 Nov. 02, 2005 Page 388 of 500
REJ09B0027-0500
Register
Name Reset Active Sleep Subactive Subsleep Standby Module
TCORA Initialized — — Initialized Initialized Initialized Timer V
TCORB Initialized — — Initialized Initialized Initialized
TCNTV Initialized — — Initialized Initialized Initialized
TCRV1 Initialized — — Initialized Initialized Initialized
SMR Initialized — — Initialized Initialized Initialized SCI3
BRR Initialized — — Initialized Initialized Initialized
SCR3 Initialized — — Initialized Initialized Initialized
TDR Initialized — — Initialized Initialized Initialized
SSR Initialized — — Initialized Initialized Initialized
RDR Initialized — — Initialized Initialized Initialized
ADDRA Initialized — — Initialized Initialized Initialized A/D converter
ADDRB Initialized — — Initialized Initialized Initialized
ADDRC Initialized — — Initialized Initialized Initialized
ADDRD Initialized — — Initialized Initialized Initialized
ADCSR Initialized — — Initialized Initialized Initialized
ADCR Initialized — — Initialized Initialized Initialized
PWDRL Initialized — — — — — 14bit PWM
PWDRU Initialized — — — — —
PWCR Initialized — — — — —
TCSRWD Initialized — — — — — WDT*
2
TCWD Initialized — — — — —
TMWD Initialized — — — — —
ABRKCR Initialized — — — — — Address break
ABRKSR Initialized — — — — —
BARH Initialized — — — — —
BARL Initialized — — — — —
BDRH Initialized — — — — —
BDRL Initialized — — — — —
PUCR1 Initialized — — — — — I/O port
PUCR5 Initialized — — — — —
PDR1 Initialized — — — — —