Datasheet

Rev.5.00 Nov. 02, 2005 Page 491 of 500
REJ09B0027-0500
Main Revisions and Additions in this Edition
Item Page Revision (See Manual for Details)
Preface vi, vii Notes:
When using the on-chip emulator (E7, E8) for H8/3687
program development and debugging, the following restrictions
must be noted.
1. The NMI pin is reserved for the E7 or E8, and cannot be
used.
3. Area H'D000 to H'DFFF is used by the E7 or E8, and is not
available to the user.
5. When the E7 or E8 is used, address breaks can be set as
either available to the user or for use by the E7 or E8. If
address breaks are set as being used by the E7 or E8, the
address break control registers must not be accessed.
6. When the E7 or E8 is used, NMI is an input/output pin
(open-drain in output mode), P85 and P87 are input pins,
and P86 is an output pin.
7. Use channel 1 of the SCI3 (P21/RXD, P22/TXD) in on-
board programming mode by boot mode.
Note has been deleted.
Section 1 Overview
Figure 1.2 Internal Block
Diagram of H8/3687N
(EEPROM Stacked
Version)
4
PB0/AN0 PB1/AN1 PB2/AN2 PB3/AN3 PB4/AN4 PB5/AN5 PB6/AN6 PB7/AN7
A/D converter
Address busAddress bus
Address bus
Data bus (upper)
POR/LVD
(optional)
Port B
AV CC
Section 5 Clock Pulse
Generators
Figure 5.3 Typical
Connection to Crystal
Resonator
70
1
2
C
1
C
2
OSC
OSC
21
C = C = 10 to 22 pF
Figure 5.5 Typical
Connection to Ceramic
Resonator
71
OSC
1
OSC
2
C
1
C
2
C
1
= 5 to 30 pF
C
2
= 5 to 30 pF