Datasheet

Rev.5.00 Nov. 02, 2005 Page 493 of 500
REJ09B0027-0500
Item Page Revision (See Manual for Details)
13.4.9 Timer Z Output
Timing
Figure 13.44 Example of
Output Disable Timing of
Timer Z by Writing to
TOER
238
T 1 T 2
Address bus
TOER address
Timer Z
output pin
Timer Z output
I/O port
I/O port
Timer output
φ
Figure 13.45 Example of
Output Disable Timing of
Timer Z by External
Trigger
238
TOER
Timer Z
output pin
Timer Z output
I/O port
Timer Z output I/O port
N
φ
H'FF
Bit Bit Name Description
4 TCSRWE Timer Control/Status Register WD Write
Enable
Section 14 Watchdog
Timer
14.2.1 Timer
Control/Status Register
WD (TCSRWD)
252
Bit Bit Name Description
3 STOP Stop Condition Detection Flag
[Setting conditions]
• In master mode, when a stop condition is
detected after frame transfer
• In slave mode, when a stop condition is
detected after the general call address or
the first byte slave address, next to
detection of start condition, accords with
the address set in SAR
Section 17 I
2
C Bus
Interface 2 (IIC2)
17.3.5 I
2
C Bus Status
Register (ICSR)
314
17.7 Usage Notes 336 Added
Section 18 A/D Converter
18.3.1 A/D Data Registers
A to D (ADDRA to
ADDRD)
340 Therefore byte access to ADDR should be done by reading the
upper byte first then the lower one. Word access is also
possible. ADDR is initialized to H'0000.