Datasheet

Section 13 Timer Z
Rev.5.00 Nov. 02, 2005 Page 209 of 500
REJ09B0027-0500
2. Input capture signal timing
Input capture on the rising edge, falling edge, or both edges can be selected through settings in
TIOR. Figure 13.18 shows the timing when the rising edge is selected. The pulse width of the
input capture signal must be at least two system clock (φ) cycles.
TCNT
Input capture signal
Input capture input
GR
N
N
φ
Figure 13.18 Input Capture Signal Timing