Datasheet

Section 17 I
2
C Bus Interface 2 (IIC2)
Rev.5.00 Nov. 02, 2005 Page 305 of 500
REJ09B0027-0500
Vcc Vcc
SCL in
SCL out
SCL
SDA in
SDA out
SDA
SCL
(Master)
(Slave 1)
(Slave 2)
SDA
SCL in
SCL out
SCL
SDA in
SDA out
SDA
SCL in
SCL out
SCL
SDA in
SDA out
SDA
Figure 17.2 External Circuit Connections of I/O Pins
17.2 Input/Output Pins
Table 17.1 summarizes the input/output pins used by the I
2
C bus interface 2.
Table 17.1 I
2
C Bus Interface Pins
Name Abbreviation I/O Function
Serial clock SCL I/O IIC serial clock input/output
Serial data SDA I/O IIC serial data input/output
17.3 Register Descriptions
The I
2
C bus interface 2 has the following registers:
• I
2
C bus control register 1 (ICCR1)
• I
2
C bus control register 2 (ICCR2)
• I
2
C bus mode register (ICMR)
• I
2
C bus interrupt enable register (ICIER)
• I
2
C bus status register (ICSR)
• I
2
C bus slave address register (SAR)
• I
2
C bus transmit data register (ICDRT)